This circuit is supposed to divide clk signal by 3. However, when I try to simulate I get this issue:

Analysis: Time step too small; time = 1e-07, timestep = 1.2207e-19: trouble with dflop-instance a5

I've tried changing pulse parameters but nothing seems to work

 

hi blah,
Welcome to AAC.
Please post your LTSpice asc file.
E

 

hi blah,
Add the options command line to the asc circuit.
Also set the Vcc voltages for the digital circuits
E

 

hi blah,
Add the options command line to the asc circuit.
Also set the Vcc voltages for the digital circuits
E
View attachment 343134

Thank you so much!

 

Thank you so much!

hi blah,
Add the options command line to the asc circuit.
Also set the Vcc voltages for the digital circuits
E
View attachment 343134

Actually just a follow up, would there be a way to make this circuit divide the freq by 3 as well as the duty cycle by 3

 

hi blah,
You have Clock frequency of 1megHz, divided giving a frequency of 333,333.33Hz, The ratio of those two frequencies cannot give a 1:1 mark/space result.
E

 

You could double the frequency, divide by 3 then by 2, but the resulting mark-space ratio is only as good as the input make-space ratio.