Here's my suggestion.
NAND gates are CD4093B.
I could have made a T-FF with the remaining CD4093B's (whole circuit using only one chip) but I think the CD4013 will provide better symmetry.
Uses two chips including the CD4013B. Probably run better at 12v.

View attachment 259040

Not wanting to be overly critical, but I don't see the requested 10% dead time in that trace. It should look more like:



You need to gate the outputs of the FlipFlop with the 80% wide 1MHz incoming clock (or its inverse if is 20% wide as here) eg:



Edit: fixed missing attachment...

 

Not wanting to be overly critical, but I don't see the requested 10% dead time in that trace. It should look more like:
You need to gate the outputs of the FlipFlop with the 80% wide 1MHz incoming clock (or its inverse if is 20% wide as here) eg:

That's a way to do it...but I didn't see a request from the TS for dead time.

 

It is implied d by 40% duty cycle and 180° Phase shift.

Bob

 

It is implied d by 40% duty cycle and 180° Phase shift.

Bob

I understood it differently.
Two clocks, 180 degrees out of phase, each with 40% duty cycle.
If the TS stated "for a mosfet driver", then dead time would be implied, to me anyway...

 

I understood it differently.
Two clocks, 180 degrees out of phase, each with 40% duty cycle.
If the TS stated "for a mosfet driver", then dead time would be implied, to me anyway...

Assuming the 40% (0.8uS) is in the 1st half of each 2uS interval on each phase then the description forces a 0.2uS deadtime between phases. There was no statement regarding "mosfet driver" and not all drivers generate dead-time anyway. But your solution doesn't generate 40% duty cycle on both phases, it generates 40% + its inverse, although I accept there is some ambiguity in the request.

 

It is implied d by 40% duty cycle and 180° Phase shift.

Yeah, I wondered about that. The initial question is ambiguous in more than one way.

ak

 

There was no statement regarding "mosfet driver" and not all drivers generate dead-time anyway.

I know....but it would helped.

But your solution doesn't generate 40% duty cycle on both phases, it generates 40% + its inverse, although I accept there is some ambiguity in the request.

It generates 40% duty on each phase, which is what I intended, but i agree, not relative to each output waveform.

We really need to hear from the TS...

 

I might have missed this
but Is this by any chance for a switch mode power supply controller ?

Any reason your not using an off the shelf SMPS controller ?

 

I might have missed this
but Is this by any chance for a switch mode power supply controller ?

Any reason your not using an off the shelf SMPS controller ?

I think I might have mentioned the UCC3808 and LM3525 back in post #6, but no-one followed it up.

 

I think I might have mentioned the UCC3808 and LM3525 back in post #6, but no-one followed it up.

@Ian0
I missed it as well !! sorry

 

I think I might have mentioned the UCC3808 and LM3525 back in post #6, but no-one followed it up.

Didn't the TS say he didn't have the 5v they needed....

 

Didn't the TS say he didn't have the 5v they needed....

Are there not other parts that perform the SMPS driver that meet the requirement the OP wanted ?
@Irving

 

Are there not other parts that perform the SMPS driver that meet the requirement the OP wanted ?
@Irving

Possibly, but IMHO it wasn't a driver he was looking for.. The requirement is unknown.