Not wanting to be overly critical, but I don't see the requested 10% dead time in that trace. It should look more like:Here's my suggestion.
NAND gates are CD4093B.
I could have made a T-FF with the remaining CD4093B's (whole circuit using only one chip) but I think the CD4013 will provide better symmetry.
Uses two chips including the CD4013B. Probably run better at 12v.
View attachment 259040
You need to gate the outputs of the FlipFlop with the 80% wide 1MHz incoming clock (or its inverse if is 20% wide as here) eg:
Edit: fixed missing attachment...