IIRC there is a maximum time between refresh cycles. We never pushed up against that limit very hard. We did have smaller chips by at least several orders of magnitude.Yes, I imagined it could be a problem with refreshment times. I'm driving my SDRAM with an FPGA and I have a specific FSM to do so which also includes the parameterization of the refresh times. Having a lower clock I think you have to increase the refresh rate, do it more times than what is established by the nominal data. Is my reasoning correct?