Hi to all,
I'm driving MT48LC16M16A2P-6A_IT_G_TR RAM with an open-source VHDL controller on an Efinix Trion T120 FPGA, but it doesn't seem to work properly; sometimes it writes and reads properly, other times it doesn't and crashes or reads (or perhaps writes) inconsistent data.
The FPGA clock is 100MHz, provided by the PLL (I can't go higher because the reference frequency is only 25MHz). The controller parameters (in nanoseconds) are as follows:


T_DESL : real := 200000.0; -- startup delay
T_MRD : real := 20.0;
T_RC : real := 60.0; -- row cycle time
T_RCD : real := 18.0; -- RAS to CAS delay
T_RP : real := 18.0; -- precharge to activate delay
T_WR : real := 12.0; -- write recovery time
T_REFI : real := 7000.0 -- average refresh interval


I think the problem lies with these values, but aside from a few, I can't find the others in the datasheets.

Note that the same code (with slightly different parameters) works fine on another type of SDRAM.

Could you please offer some suggestions?

Thanks everyone.

 

Without the knowledge of the core you are using it is difficult to know if the HDL block is designed to work with this memory. For the worst case scenario suppose it is not.

In general, if the timing is not explicitly specified, you can deduce it from other parameters and from the timing diagrams.

 

Hi to all,
I'm driving MT48LC16M16A2P-6A_IT_G_TR RAM with an open-source VHDL controller on an Efinix Trion T120 FPGA, but it doesn't seem to work properly; sometimes it writes and reads properly, other times it doesn't and crashes or reads (or perhaps writes) inconsistent data.
The FPGA clock is 100MHz, provided by the PLL (I can't go higher because the reference frequency is only 25MHz). The controller parameters (in nanoseconds) are as follows:


T_DESL : real := 200000.0; -- startup delay
T_MRD : real := 20.0;
T_RC : real := 60.0; -- row cycle time
T_RCD : real := 18.0; -- RAS to CAS delay
T_RP : real := 18.0; -- precharge to activate delay
T_WR : real := 12.0; -- write recovery time
T_REFI : real := 7000.0 -- average refresh interval


I think the problem lies with these values, but aside from a few, I can't find the others in the datasheets.

Note that the same code (with slightly different parameters) works fine on another type of SDRAM.

Could you please offer some suggestions?

Thanks everyone.

fpga design is not software ,
its a guess, but
your fpga needs to meet timming constraints as well as work correctly,
these constraints are not generally part of ip thats not provided by the chip manufacturer , as every manufacturer seems to have a variation on the standard timming format.
note , these constraints are separate to the ddr parameters you mention above .