I'm building a gate with Skywater 130 technology.
I'm using a 125MHz clock signal (8ns) with rise and fall times of 1ps (I use XSchem and ngspice for simulation)
Measuring the current draw, I noticed that there are sharp peaks (almost 4mA) corresponding to the clock (or signal) transitions.
I noticed that by slowing the signal clock rise and fall times to about 100ps, the peak draw decreases to about 50uA, making them much more manageable.
My question is: in reality, what rise and fall times does a 125MHz clock have? What values should I use to make the simulation more realistic?

 

What are the required rise and fall times for the input(s) it is driving?

 

I'm building a gate with Skywater 130 technology.
I'm using a 125MHz clock signal (8ns) with rise and fall times of 1ps (I use XSchem and ngspice for simulation)
Measuring the current draw, I noticed that there are sharp peaks (almost 4mA) corresponding to the clock (or signal) transitions.
I noticed that by slowing the signal clock rise and fall times to about 100ps, the peak draw decreases to about 50uA, making them much more manageable.
My question is: in reality, what rise and fall times does a 125MHz clock have? What values should I use to make the simulation more realistic?

yes, when you switch , the inherent capacitance of the circuit has to be charged / discharge.
the faster you have to change that charge , the more current you need.
two "rules of thumb"
a. the thing your driving defines whats required.
b. if not stated, expected is in order of 10 to 5% of the period .

 

a. the thing your driving defines whats required

Which is why i asked the question above.

 

What are the required rise and fall times for the input(s) it is driving?

I don't think I have an answer to this, maybe I'm wrong but I'm planning to have a frequency of 125 MHz on the first level and at most 3 cascaded gate levels.

 

Then I guess you are out of luck.

 

Sorry, I'm new to this, I don't understand what you mean. Could you please explain?

 

your 125MHz clock is meant to drive something. and so far only you know what that something is. "3 gates" is just not specific... is any of them using Schmidt trigger?

gates are basic elements. they can be used to make larger elements like flip flops, registers, endoders, decoders, etc. they all will have propagation times. so if you have ARB or filters or similar you can soften the edges and try to feed 125MHz sine wave and see if they still work the way you expected (probably not). then try to make the rise and fall time shorter and shorter until they do work. maybe for your use case 2500ps is fine. maybe it is 25ps... whatever the number that will be the value that you are looking for.

 

Which is why i asked the question above.

my apologies, the posts crossed, did not mean to pinch your part of the answer without a cross reference to you.

 

I don't think I have an answer to this, maybe I'm wrong but I'm planning to have a frequency of 125 MHz on the first level and at most 3 cascaded gate levels.

so this is totaly inside the asic ?

 

steep learning curve.
pdf page 51 of 210
High-Speed Serial I/O Made Simple

The standard used is LV-PECL
but having various output types
EG-2121CA_en.pdf

 

how is that getting closer to the t_rise and t_fall? it only shows stability values, not how steep the flanks are.
period is 8ns so each flank could be as long as 4ns.

 

how is that getting closer to the t_rise and t_fall? it only shows stability values, not how steep the flanks are.
period is 8ns so each flank could be as long as 4ns.

Sorry , which post is this wrt ?

 

steep learning curve.
pdf page 51 of 210
High-Speed Serial I/O Made Simple

 

your 125MHz clock is meant to drive something. and so far only you know what that something is. "3 gates" is just not specific... is any of them using Schmidt trigger?

gates are basic elements. they can be used to make larger elements like flip flops, registers, endoders, decoders, etc. they all will have propagation times. so if you have ARB or filters or similar you can soften the edges and try to feed 125MHz sine wave and see if they still work the way you expected (probably not). then try to make the rise and fall time shorter and shorter until they do work. maybe for your use case 2500ps is fine. maybe it is 25ps... whatever the number that will be the value that you are looking for.

My actual problem is current draw (and therefore gate power dissipation).
I'm simulating an inverter with dynamic CMOS technology, which therefore requires a clock. I'm providing the clock in the simulation and have defined its characteristics (1 ps rise and fall time - 8ns period), and by doing so, I'm getting extremely high current peaks in the simulation (4mA).
So I'd like to adjust the clock parameters so that they closely match a real clock, undoubtedly provided by a PLL. For this reason, I was wondering if 100 ps rise and fall times are realistic for a real 125 MHz clock signal.

 

i am not sure but... as far as i recall PC architecture, DRAM gets controlled by a chipset (including clock, refresh etc.).
rise and fall time of an oscillator may be something else but looking at edges of signals produced by chipset would be a close match. since chipset has to supply different frequencies and timing, for different parts of the system, i would expect that raw clock signal (as supplied by oscillator) would be cleaned up by a Schmidt trigger before being passed through the rest of the logic. and not just clock, DRAM cells are basically capacitors that get charged and discharged at different intervals. the slower refresh the deeper the discharge. so levels can be different, and each and every bit will need to be going through similar process (Schmidt trigger). you are not going to pass an analog value to rest of the computer.

 

@mos_6502

this is still a bit ambigious.
are you designing a chip / asic which receives this 125 Mhz clock, or are you designing something that produces this 125 Mhz clock ?

or what?

im thinking your designing an asic , and younare receiving the clock.

please tell us if thats correct.

so on a real chip, the external clock, 125 Mhz is a very common frequency ,

an external clock chip / oscilator of 125 Mhz fall into two broad types, single ended and differential.

single ended, would be say 3v3 or 1v8 cmos levels, with rise fall times of around 1 ns. These are general purpose , but have a higher jitter than the differential.

differential, would typically be lvds .
these have rise / fall times of order of 100 ps, and are used for things like Ghz serial links , due to the low jitter, but need two pins on the chip , and termination,

yes, other single ended and differential exist ..

on your chip, the current draw is when all the transistors switch , and they have to charge / discharge all that capacitance inside the chip.
if you use a slower rise / fall inside the chip, this is done by selecting different driver capable macros . effectively your drivers output resistance with the capacitance of the silicon layout, forms a low pass filter, slowing the edge.

the downside, is you add more effective uncertainty, typicaly refered to as jitter, on when you transistors switch. you need to ensure your data / clock meet timing over Process Voltage and Temprature , the slower the clockm edge is, the harder that can become for any speed circuit,

 

this is still a bit ambigious.
are you designing a chip / asic which receives this 125 Mhz clock, or are you designing something that produces this 125 Mhz clock ?

or what?

im thinking your designing an asic , and younare receiving the clock.

please tell us if thats correct.

Yes, I'm designing a chip that will receive a 125 MHz external clock.

[...]

differential, would typically be lvds .
these have rise / fall times of order of 100 ps, and are used for things like Ghz serial links , due to the low jitter, but need two pins on the chip , and termination,
[...]

It would be interesting to have a differential one; I'll definitely have to use a reverse clock inside the chip, and knowing that there's an external circuit that implements it is great news.

And in any case, I'm now thinking of using a delay of about 100 ps in my simulation, which could be similar to that of a real oscillator.

[...]
the downside, is you add more effective uncertainty, typicaly refered to as jitter, on when you transistors switch. you need to ensure your data / clock meet timing over Process Voltage and Temprature , the slower the clockm edge is, the harder that can become for any speed circuit,

For now, I'm just simulating a simple gate; I imagine things will get much more complex when the circuit has multiple gates. I'll take everything into account and will definitely post some more questions here on the forum.
Unfortunately, I don't have access to advanced design software, and I'm using the Skywater130 package with xschem and ngspice for simulation.

 

Yes, I'm designing a chip that will receive a 125 MHz external clock.

Why can't you use the predefined input cell of the manufacturer? Usually they have defined timing parameters to ensure a correct functionality. Or are you the unlucky guy who has to define these parameters?

 

I'm building a gate with Skywater 130 technology.
I'm using a 125MHz clock signal (8ns) with rise and fall times of 1ps (I use XSchem and ngspice for simulation)
Measuring the current draw, I noticed that there are sharp peaks (almost 4mA) corresponding to the clock (or signal) transitions.
I noticed that by slowing the signal clock rise and fall times to about 100ps, the peak draw decreases to about 50uA, making them much more manageable.
My question is: in reality, what rise and fall times does a 125MHz clock have? What values should I use to make the simulation more realistic?

Where are your present 1 ps rise and fall times coming from? Is that just what you have set in some ideal simulation source?

One way to get an good idea of realistic edge rates is to use realistic circuits to produce them.

Use your ideal clock source to drive a buffer made using your SKY130 libraries. Have that drive another buffer and have that buffer driving the number of other buffers that you want to have as your fanout maximum.

Then look at the rise/fall times of the signal at the output of the second buffer.

As a quick ballpark guess, though, starting off with rise and fall times that are about 5% to 10% of the shortest edge-to-edge period is good enough for many applications. For 125 MHz, that would yield rise/fall times in the 200 ps to 400 ps range. A given application may be driven by considerations that require either faster edges than that, or slower edges, but you can start here and then do the simulations you need to determine whether it is good enough and, if not, whether you need to go faster or slower for your needs.