Adjust the rise and fall time from a driver

D.Vesa

Joined May 3, 2015
6
I have hard time understanding the specifications from this gate driver UCC27511A-Q1 and how to adjust a rise and fall time for my NMOS.

I understand that for a period of 0.5us ( 2000kHz ) it can supply a source current of 4A and a sink current of 8A.

The internal resistance specified are:

In my particular project I want to use Vgs = 12V the activate the FET and I want to adjust the rising and fall time of the switching and here is the problem that I do not understand. There is an example with a Cload that have a specific rise and fall time.

Does the CLoad emulates the parasitic capacitance that is usually found in FET datasheet as Q gate charge? ( in my project I need ~80 nano Coulombs )

If so, if my understanding is correct for 0.5us and 4 Amps results 2 micro Coulomb.

For the situation where is used a Cload of 1.8 nF I calculated the Power needed but I have a hard time understanding how to adjust my resistances for a custom rise fall time. ( let's say that I want a rise of 100 ns )

crutschow

Joined Mar 14, 2008
32,840
Why do you want to adjust the rise and fall times, which are usually left as is?

D.Vesa

Joined May 3, 2015
6
Why do you want to adjust the rise and fall times, which are usually left as is?
Because I know that it is possible and I want to be able to understand the dynamic relation between the Q gate charge from any NMOS datasheet and the source and sink currents from a driver.

What if I want to have a better Rds_ON on my transistor and for that I need to supply 15V instead of 12V ( like in the driver example ).

As you can see the driver range is maximum 20V. One really simple example of this dynamic would help me a lot.

crutschow

Joined Mar 14, 2008
32,840
if I want to have a better Rds_ON on my transistor and for that I need to supply 15V instead of 12V
Generally there is little on no reduction in Rds(ON) with a Vgs >10V, and that is not affected by the rise/fall times at the gate.
If you want to see the results the rise/fall time variation then do a SPICE simulation with a voltage source, which allows easy variation of those simulated times.

D.Vesa

Joined May 3, 2015
6
Generally there is little on no reduction in Rds(ON) with a Vgs >10V, and that is not affected by the rise/fall times at the gate.
If you want to see the results the rise/fall time variation then do a SPICE simulation with a voltage source, which allows easy variation of those simulated times.
Let's take this example from a datasheet FET. As you can see that there is slightly variation especially when you have a drain current near its design limit.

I understand that in reality there is parasitic inductance and you can find them in SPICE models that gives the ringing effect and that the voltage rise on Vgate is non linear. Usually you treat them as a first order approximation, using only the Cies when you want to do "pocket calculations".
Ideal: let's say that Vgs it's a square wave for which I can use avg. How can I adjust the rise/fall by adding external resistor? How do I interpret de Gate Driver's datasheet? What is that Cload which is mentioned in Gate Driver's datasheet?
How do I scale the 4A source for other periods of rise time? I would really appreciate an example. I am begging you.

LowQCab

Joined Nov 6, 2012
3,446
Just create this model in your favorite Circuit-Simulator,
and then add varying Resistances to the Gate ............
.
.
.

.

crutschow

Joined Mar 14, 2008
32,840
Add a resistor in series with the gate.
Values in the kΩ region should work, depending upon the gate capacitance of the MOSFET you are testing.

StefanZe

Joined Nov 6, 2019
178
Let's take this example from a datasheet FET. As you can see that there is slightly variation especially when you have a drain current near its design limit.

View attachment 287409

I understand that in reality there is parasitic inductance and you can find them in SPICE models that gives the ringing effect and that the voltage rise on Vgate is non linear. Usually you treat them as a first order approximation, using only the Cies when you want to do "pocket calculations".
Ideal: let's say that Vgs it's a square wave for which I can use avg. How can I adjust the rise/fall by adding external resistor? How do I interpret de Gate Driver's datasheet? What is that Cload which is mentioned in Gate Driver's datasheet?
How do I scale the 4A source for other periods of rise time? I would really appreciate an example. I am begging you.
The rise and fall time depends on the Cgate and the internal driver resistor + your external gate resistor.
Cload ist the capacitor used in the tests for the driver.
The current source is depended on the load you are driving. With an external resistor you can change the driving current. The 4A is only the maximum current not the actual current (the actual current depends on your design, e.g. gateresistor and mosfet).