Hi All,

I have designed a gate drive circuit for a Silicon carbide module, and all works well... almost.

Commonly seen in theory for the required gate driver current to achieve a rise/fall time of FET input capacitance is: Qgd/T = Ig where these are the gate charge, transition time, and gate drive current respectively.

This would dictate that a gate driver capable of sourcing/sinking 10A would allow us to charge and discharge ~1135nC in approximately 113.5nS. All good.

Another equation for charging a capacitor through a resistor, tool here for simplicity: Capacitor Charge and Time Constant Calculator - Engineering Calculators & Tools (allaboutcircuits.com)

Dictates that the time taken to go from 10-90 percent of the voltage on a capacitor is around 2 time constants. Assuming a gate resistance of 1.2Ohms, and a 19V gate voltage swing, we should be able to drive around 15A of current in a practical application.

To calculate the actual, effective capacitance to be driven (rather than the stated "input capacitance" in the data sheet, I will use C = Q/V, which is around 60nF. This should give a better representation of performance including Miller charge effect, etc. I am not yet in a position to drive the actual MOSFET, so using a C0G/NP0 capacitor as the load to get a good feeling of what we would expect.

Now, the tool (and my practical results) show rise times from 150ns-200ns - significantly slower than would be dictated by the first equation.

What am I missing, or what am I doing wrong? Why does one equation lead to significantly different results than the other? Have I gone wrong somewhere in the calculation of the equivalent capacitance? The data sheet states input capacitance is 31nF or so, but that is at a particular operating condition only.

Looking forward to a great discussion. SIC.

 

As you know the rise and fall characteristics of a MOSFET gate are far from linear. There are multiple interactions between the inter-electrode capacitances and the changing impedance of the channel that contribute to this apparent behavior. What is true for one device may not be true for another device with supposedly similar characteristics. I don't envy you in your struggle.

One more thing. The COG/NPO capacitor will NEVER behave the same way as channel transitioning from off to on or vice versa.

 

As you know the rise and fall characteristics of a MOSFET gate are far from linear. There are multiple interactions between the inter-electrode capacitances and the changing impedance of the channel that contribute to this apparent behavior. What is true for one device may not be true for another device with supposedly similar characteristics. I don't envy you in your struggle.

One more thing. The COG/NPO capacitor will NEVER behave the same way as channel transitioning from off to on or vice versa.

Yep, we’ve had this discussion or similar before, and I finally thought I’d got the hang of it!

It does seem to come down to non-linear behaviour, the effective capacitance is always changing and slew rates will change during the switching period.

But all that confuses me, still, is how many say rise time will be 1135e-9/10 = 113.5nS, but physics tells us that the rise time of a 60nF capacitor charged up to 1135e-9 with 10Amps of current. The discrepancy is huge, around 160nS - makes a huge difference.
In my head, at least, the maximum rise times of the gate drive should align with the latter theory, as I simply do not see how it could be any faster than this.

 

Hi All,

I have designed a gate drive circuit for a Silicon carbide module, and all works well... almost.

Commonly seen in theory for the required gate driver current to achieve a rise/fall time of FET input capacitance is: Qgd/T = Ig where these are the gate charge, transition time, and gate drive current respectively.

This would dictate that a gate driver capable of sourcing/sinking 10A would allow us to charge and discharge ~1135nC in approximately 113.5nS. All good.

Another equation for charging a capacitor through a resistor, tool here for simplicity: Capacitor Charge and Time Constant Calculator - Engineering Calculators & Tools (allaboutcircuits.com)

Dictates that the time taken to go from 10-90 percent of the voltage on a capacitor is around 2 time constants. Assuming a gate resistance of 1.2Ohms, and a 19V gate voltage swing, we should be able to drive around 15A of current in a practical application.

To calculate the actual, effective capacitance to be driven (rather than the stated "input capacitance" in the data sheet, I will use C = Q/V, which is around 60nF. This should give a better representation of performance including Miller charge effect, etc. I am not yet in a position to drive the actual MOSFET, so using a C0G/NP0 capacitor as the load to get a good feeling of what we would expect.

Now, the tool (and my practical results) show rise times from 150ns-200ns - significantly slower than would be dictated by the first equation.

What am I missing, or what am I doing wrong? Why does one equation lead to significantly different results than the other? Have I gone wrong somewhere in the calculation of the equivalent capacitance? The data sheet states input capacitance is 31nF or so, but that is at a particular operating condition only.

Looking forward to a great discussion. SIC.

Hi,

The thing is, many of these calculations are approximate because the more exact analysis is more complicated overall.
As I pointed out in another thread somewhere, the charge characteristic is exponential:
ig=Vg/Rg*e^(-t/RC)

and so this requires more work. Because things change, there are four different charge regions you have to consider if you want to get more precise results. In the end it may still be questionable if it works out any better.

What you should do is read a better application note that explains this in more detail. You could then try to make more sense of it.

You could find this pdf see if this helps:
GateChargeSwitchingTimes-APT0103.pdf

Motorola had some good information on this too in one of their data books, you could look for that also.