In a MOSFET power module (XM3 450Amp by Wolfspeed, here: https://www.wolfspeed.com/xm3-power-module-family/

the input capacitance is stated as 38nF. The total gate charge however is stated as 1330nC. For a gate voltage swing of 19V (+15V/-4V) the charge for the capacitor Q = CV = 722nC.

My question is, where does the rest of this gate charge come from? I have been testing the switching rise and fall times of my driver with a 38nF load and have managed to get very good results, but I am unsure whether I will expect the same performance when connecting the actual module. The theoretical capacitor charge, which should encompass both CGD and CGS, is almost half that than would be expected in the data sheet for total gate charge.

This may also skew my results in regards to power dissipation - if the total gate charge is twice or so of these results then the power dissipation may also be double when connecting to the module.

It may be worth noting that the rise and fall times across this capacitor seem to agree well with the equation T= QT/Ipk where T is the rise time, QT is the total gate charge, and Ipk is the peak output current of the isolated gate driver. So I am slightly confused about it. Thanks!

 

My question is, where does the rest of this gate charge come from?

Much of it comes from the Miller capacitance effect between the drain and gate.
The charge transfer from the gate-drain capacitance is determined by its capacitance times the drain voltage change as it turns on.
So the larger the drain voltage change as it turns on, the more gate charge is needed from the gate drive circuit.

This charge transfer be seen as a plateau in the gate voltage during the MOSFET turn-on for a gate drive with a finite impedance.
Below is an LTspice simulation to show this effect.
Note that the gate voltage (yellow trace) initially rises while charging the gate capacitance until it reaches the MOSFET threshold voltage, where the MOSFET starts to turn until and the Miller charge is added.
When the transistor is fully turned on (blue and red traces), and all the Miller charge is transferred at about 0.56µs, the gate voltage then continues to rise as the gate capacitance is further charged.
The purple trace shows the current into the gate.

 

Perfect answer - this is exactly what I assumed. However one thing still confuses me is the input capacitance should encompass both the CGD and the CGS - so how come this capacitance doesn’t agree with the actual gate charge required to turn the device on and off?

Even though it is not equal, how come my gate driver power dissipation is equal to that which it should dissipate with >1000nC of charge despite me only modelling it with a simple C0G capacitor? I shouldn’t really experience the Miller effect with this configuration, which I of course am not, but I am just trying to figure out how the gate driver performance will change when connected to the actual device during switching when the Miller effect is experienced.
In my head, the actual “equivalent capacitor” should have the same amount of charge CV required to fully turn the device on and off with the Miller effect accounted for - which would require a capacitor of around twice the value?

Much of it comes from the Miller capacitance effect between the drain and gate.
The charge transfer from the gate-drain capacitance is determined by its capacitance times the drain voltage change as it turns on.
So the larger the drain voltage change as it turns on, the more gate charge is needed from the gate drive circuit.

This charge transfer be seen as a plateau in the gate voltage during the MOSFET turn-on for a gate drive with a finite impedance.
Below is an LTspice simulation to show this effect.
Note that the gate voltage (yellow trace) goes to just above the MOSFET threshold voltage until the transistor is fully turned on (blue and red traces) and all the Miller charge is transferred at about 0.56µs.
The purple trace shows the current into the gate.

View attachment 300727

 

Even though it is not equal, how come my gate driver power dissipation is equal to that which it should dissipate with >1000nC of charge despite me only modelling it with a simple C0G capacitor?

So what is the gate voltage swing, the capacitance value modeled, and the power dissipation you measured?

 

So what is the gate voltage swing, the capacitance value modeled, and the power dissipation you measured?

Bc

So what is the gate voltage swing, the capacitance value modeled, and the power dissipation you measured?

Gate voltage swing is 19V (+15/-4), capacitance modelled is 33nF, power dissipation is around 2.5W at 100kHz. All rise and fall times agree with theory. So from this standpoint it would certainly look to agree with the 1330nC figure and the input capacitance. I’m not sure if I’m just being stupid and it since one switching cycle includes both a charge and a discharge, the total charge is equal to twice that of Q=CV. I’m prone to making such silly mistakes but I want to make sure!

 

Gate capacitance in a MOSFET is highly nonlinear, so that 38 nF in the datasheet is the capacitance under some specific set of conditions, which hopefully the data sheet provides. The capacitance increases as the gate is turned on harder, so if the 38 nF happens to be measured when the device is in cutoff, the effective capacitance as you go from off to on is going to be quite a bit greater. Total gate charge, on the other hand, is the charge transferred to/from the gate between a set of specific conditions (again, hopefully which are specified).

 

Gate capacitance in a MOSFET is highly nonlinear, so that 38 nF in the datasheet is the capacitance under some specific set of conditions, which hopefully the data sheet provides. The capacitance increases as the gate is turned on harder, so if the 38 nF happens to be measured when the device is in cutoff, the effective capacitance as you go from off to on is going to be quite a bit greater. Total gate charge, on the other hand, is the charge transferred to/from the gate between a set of specific conditions (again, hopefully which are specified).

The data sheet seems to suggest that the input capacitance is fairly constant with drain-source voltage. See attached. However the reverse transfer capacitance shows a fairly large dependence.

How does this affect average gate driver power consumption? I still don’t understand how my experiments show 2.5W of dissipation in the driver for 33nF capacitive load - this would agree with the 1330e-9 gate charge despite not taking into account any non-linear effects.

should I expect that the gate drive losses do not change when connecting to the actual FET? But that the rise-fall time may be slowed as the drain-source voltage decreases?

 

The big factor isn't the drain-source voltage, but rather the gate-source voltage. In the figure, I'm assuming that Vac is the variation in Vgs and it is only 25 mV (just enough to give them a signal to work with).

 

Gate voltage swing is 19V (+15/-4), capacitance modelled is 33nF, power dissipation is around 2.5W at 100kHz.

The theoretical power dissipation for charging and discharging a capacitance is fCV² = 100k * 33nF * 19² = 1.37W so I don't see how your are dissipating 2.5W.
How are you measuring that power?

 

The big factor isn't the drain-source voltage, but rather the gate-source voltage. In the figure, I'm assuming that Vac is the variation in Vgs and it is only 25 mV (just enough to give them a signal to work with).

Understood. Thank you. I can’t seem to find the relationship between the capacitances and the gate drive voltage. But I suppose the question still remains. Assuming I drive the actual FET with the exact same gate-source voltage and gate current, can I safely assume that it will dissipate approximately the same power as the test case with a 33nF capacitor? Maybe it will be slightly higher until the device is pushed past the Miller plateau. But I would assume those effects are modelled in the gate charge quantity, which as I mentioned, is equivalent to that which I’ve observed with the capacitor test case.

 

The theoretical power dissipation for charging and discharging a capacitance is fCV² = 100k * 33nF * 19² = 1.37W so I don't see how your are dissipating 2.5W.
How are you measuring that power?

My apologies, I should have mentioned that I also have been testing an external BJT push-pull stage for additional gate current. I also meant that the input power to my isolated on-board power supply is 2.5W (12V input). I am not measuring it directly. The isolated power supply is typically 80% efficient, and the gate driver itself just drives the base capacitances of the BJT so should not dissipate a lot of power. So we are probably closer to 2W in total with the rest of the power dissipation (away from your 1.37W case) being from BJT loses and other inefficiencies.

the equation I have been using for dissipation is: Pd = QT * FSW * deltaV which should be 2.527W.

 

So we are probably closer to 2W in total with the rest of the power dissipation (away from your 1.37W case) being from BJT loses and other inefficiencies.

Most of the 1.37W will be dissipated in the BJTs.

the equation I have been using for dissipation is: Pd = QT * FSW * deltaV which should be 2.527W.

What values did you plug into that equation to get that power value?

 

Most of the 1.37W will be dissipated in the BJTs.
What values did you plug into that equation to get that power value?

100kHz, 1330nC, and 19V. I am fully aware that could be wrong though…

 

100kHz, 1330nC, and 19V. I am fully aware that could be wrong though…

Then I'm confused by this statement:

Assuming I drive the actual FET with the exact same gate-source voltage and gate current, can I safely assume that it will dissipate approximately the same power as the test case with a 33nF capacitor?

Why do you seem to think the dissipation for charging and discharging the 33nF capacitor would be the same as for 1330nC charging and discharging when it clearly is not?

 

Then I'm confused by this statement:
Why do you seem to think the dissipation for charging and discharging the 33nF capacitor would be the same as for 1330nC charging and discharging when it clearly is not?

Because the data sheet states that the input capacitance CISS is 38nF, which is equal to the CGD and CGS, so why shouldn’t the time it takes to charge and discharge the input capacitance be equal to the gate charge figure?

 

Because the data sheet states that the input capacitance CISS is 38nF, which is equal to the CGD and CGS, so why shouldn’t the time it takes to charge and discharge the input capacitance be equal to the gate charge figure?

So haven't I explained why there is a difference?
I feel like we are going in circles here.

 

So haven't I explained why there is a difference?
I feel like we are going in circles here.

you have explained that it is because of the Miller effect. Got it. I understand that.

The data sheet states that the input capacitance includes the reverse transfer capacitance - later, it is plotted as a separate quantity and is no longer considered part of the input capacitance.

I would have expected, and this is what my question was, that modelling the capacitance of the FET and testing the gate drive in this simple circuit would give somewhat of a good idea of how fast I can switch this device and how efficient the driver could be - whether my power supply had enough power.

I am still leaning towards the power dissipation being twice the Q = CV value because the NPN needs to charge and PNP needs to discharge in every switching cycle -if this were true then my results would not be too far wrong.

 

I would have expected, and this is what my question was, that modelling the capacitance of the FET and testing the gate drive in this simple circuit would give somewhat of a good idea of how fast I can switch this device and how efficient the driver could be - whether my power supply had enough power.

The single capacitor model will only give a reasonable simulation of the MOSFET gate if the capacitor is made large enough to generate the transfer of the total gate charge value.

I am still leaning towards the power dissipation being twice the Q = CV value because the NPN needs to charge and PNP needs to discharge in every switching cycle -if this were true then my results would not be too far wrong.

You can lean all you want, but that doesn't necessarily lead to the correct answer.
The energy in a charged capacitor is 1/2 CV², which is equal to the energy dissipated in the charging transistor.
Then obviously the energy dissipated in the discharging transistor has to equal to the capacitor stored energy which is also 1/2 CV².
So the dissipation in the NPN is 1/2 CV² and the dissipation in the PNP is 1/2 CV².

 

The single capacitor model will only give a reasonable simulation of the MOSFET gate if the capacitor is made large enough to generate the transfer of the total gate charge value.
You can lean all you want, but that doesn't necessarily lead to the correct answer.
The energy in a charged capacitor is 1/2 CV², which is equal to the energy dissipated in the charging transistor.
Then obviously the energy dissipated in the discharging transistor has to equal to the capacitor stored energy which is also 1/2 CV².
So the dissipation in the NPN is 1/2 CV² and the dissipation in the PNP is 1/2 CV².

Okay, I concede. Now time to figure out why my BJT drive circuit is dissipating much more power than I’d expect… Gah!

Maybe I’ll try the experiment again with a capacitor that requires 1330nC of charge - but I’m not hopeful the BJTs will enjoy it too much as they’re already getting hot…

 

Now time to figure out why my BJT drive circuit is dissipating much more power than I’d expect

So are you measuring the current and voltage going to the drive circuit to determine its power?