Why not register data on the rising edge, at the same time you clear the counter ?
then you only need one pulse ?

Ok. Then I guess I need to somehow create a delay? Maybe I don't understand but
don't you need to latch the data and then reset the counter with a delayed pulse?
Will you not loose the data if you do these two operations simultaneously?

 

Ok. Then I guess I need to somehow create a delay? Maybe I don't understand but
don't you need to latch the data and then reset the counter with a delayed pulse?

Yes and no. It depends on what you use to generate the second pulse.

If the second pulse is generated from the trailing edge of the first then there is an inherent delay of about 30ns from the gates themselves.

Do you have a 74LS123?
I can show you how to wire this and solve all your problems you are having with this circuit.

 

Yes and no. It depends on what you use to generate the second pulse.

If the second pulse is generated from the trailing edge of the first then there is an inherent delay of about 30ns from the gates themselves.

Do you have a 74LS123?
I can show you how to wire this and solve all your problems you are having with this circuit.

Hi:

Yes I do have 74LS123 s. Please show me that would make my day. Actually the year, 2020 being what it is.

I should also mention that I am using a time base of 100 Hz but in the final version I will use 1 Hz. I say this
because I understand that a control pulse width must fit inside the time base . Wasn't sure just how to say
that but I hope it was okay.

 

74123 and 74LS123 are dual retriggerable monostable multivibrators.

Reference: https://www.ti.com/lit/an/sdla006a/sdla006a.pdf

Each circuit is independent. You can choose to interchange the units as you wish, usually to simplify a PCB layout.
Each circuit as two input pins labeled as follows

PIN NAME
1 1A
2 1B
9 2A
10 2B

The circuit is triggered on a falling edge of A INPUT while B INPUT is held high.
It can also be triggered on a rising edge of B INPUT while A INPUT is held low.
Take your pick.

In the circuit below, CLOCK input to pin-9 triggers the first monostable on the falling edge of the clock.
The pulse width of the each stage is determined by its C and R values.

The second stage is triggered on the falling edge of the Q output of the first stage, delayed by about 30ns.
Use the Q and /Q outputs to LATCH and RESET with the logic desired, i.e. logic HI or logic LOW.
The output from the first stage is used to LATCH the data. The output from the second stage is used to RESET the counter.

Your pulse width is not particularly critical for your application, around 1μs would be ok.
Start off with R = 10k
C = 100pF to 1000pF

(The monostable will even work with no capacitor, just from stray capacitance, giving an output pulse about 60ns wide.)

Always measure the pulse width with the oscilloscope to confirm.

 

74123 and 74LS123 are dual retriggerable monostable multivibrators.

Reference: https://www.ti.com/lit/an/sdla006a/sdla006a.pdf

Each circuit is independent. You can choose to interchange the units as you wish, usually to simplify a PCB layout.
Each circuit as two input pins labeled as follows

PIN NAME
1 1A
2 1B
9 2A
10 2B

The circuit is triggered on a falling edge of A INPUT while B INPUT is held high.
It can also be triggered on a rising edge of B INPUT while A INPUT is held low.
Take your pick.

In the circuit below, CLOCK input to pin-9 triggers the first monostable on the falling edge of the clock.
The pulse width of the each stage is determined by its C and R values.

The second stage is triggered on the falling edge of the Q output of the first stage, delayed by about 30ns.
Use the Q and /Q outputs to LATCH and RESET with the logic desired, i.e. logic HI or logic LOW.
The output from the first stage is used to LATCH the data. The output from the second stage is used to RESET the counter.

Your pulse width is not particularly critical for your application, around 1μs would be ok.
Start off with R = 10k
C = 100pF to 1000pF

(The monostable will even work with no capacitor, just from stray capacitance, giving an output pulse about 60ns wide.)

Always measure the pulse width with the oscilloscope to confirm.

Thanks MrChips. I have some work to do. The attachment is all black. Is it the same as the diagram above?

 

Forrest Mimms and Don Lancaster are highly respected contributors to electronics. You can learn a lot by studying their publications such as TTL Cookbook by Don Lancaster. Rather than taking circuits wholesale out of their books you can further enhance your knowledge by studying each circuit and the properties and behaviour of each component.

The C-R circuit is a differentiator. The output is the derivative of the input.

View attachment 225263

Reference: https://www.electronics-tutorials.ws/rc/rc-differentiator.html

As you can observe in the diagram and on your oscilloscope there is a positive going spike generated from the rising edge of the input signal. Similarly there is a negative going spike generated from the falling edge of the input signal.

If you want to apply this signal to the input of a digital logic gate you need to pay attention to the baseline voltage, i.e. the voltage at the flat portion of the signal.

A 7400 series or 74LS00 series digital gate expects a logic low input to be lower than 0.8V and a logic high signal to be higher than 2V. Does your waveform satisfy these requirements with a sufficient margin of error?

Your quest is to turn one of those two spikes (not both at the same time) into a digital pulse.

You can bias the baseline voltage towards GND with R connected towards GND as shown. In this manner the negative spikes goes below 0V and is not seen by the following gate.

Or you can bias the baseline voltage towards Vcc with R connected towards Vcc. The positive spike goes above Vcc and is not seen by the gate following.

Experiment with the values of C and R until you get the desirable result.

Note that 7400 and 74LS00 have different input characteristics and therefore will demand different values of R.

If your input to a gate goes above its VinHigh limit, or below its VinLow limit, the gate at best will not last long.

VinH is often around Vcc + 0.5v and VinL is - 0.5v

DO not connent pulses that intentionally go above VCC or below Gnd to the input of the gate,

 

That makes good sense. Thanks.

Are you saying that the output would not have to be routed through an inverter if I used a diode?

I disconnected the inverter on the output and placed a diode across the capacitor with the cathode connected
to the end that is connected to the first inverter. That changed the circuit output to a square wave with the
same pulse width as the time base, rather than a positive pulse.

So, draw a picture of how you have the diode connected ,

Look at the signal going through the first inverter, then through the capacitor / resistor.

The signal across the resistor after the capacitor.
What would happen if you put a diode across the resistor ?
try the diode one way up, then reverse it, see what happens tot he pulse out.

Can you explain whats happening to the pulse ?