# Resolve Circuit Conflict

Joined Nov 25, 2020
68
Hi:

I am breadboarding a frequency counter. I have attached two circuits. Circuit #1 will hopefully perform
a gate control function and circuit #2 is a power-on reset for the counters. Circuit #2 works but I haven't
added #2 yet as I am concerned about a conflict since the output of both circuits will be connected to
pins 2 and 3 of each of the 74LS90 counters. Could someone please advise as to a resolution.

Thanks

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#### crutschow

Joined Mar 14, 2008
25,978
I am concerned about a conflict since the output of both circuits will be connected to
pins 2 and 3 of each 74LS47
You are well concerned about that since you can't connect the two outputs together.
You will need to add a gate to combine them.
Exactly what is the output logic sequence (truth table) of the two signals.

#### dl324

Joined Mar 30, 2015
12,207
I am concerned about a conflict since the output of both circuits will be connected to
pins 2 and 3 of each of the 74LS90 counters. Could someone please advise as to a resolution.
LS TTL can drive 20 standard loads.

From 1981 TTL databook:

#### MrChips

Joined Oct 2, 2009
22,466
As @crutschow suggests, you write out the possible logic states of circuit #1 and circuit #2 in the form of a truth table.
Then in the next column you write down what you want to happen at the counter.

You will be looking for a logical OR operation.
Finally, you apply "bubble logic" to find the correct physical gate to implement your logic

Joined Nov 25, 2020
68
You are well concerned about that since you can't connect the two outputs together.
You will need to add a gate to combine them.
Exactly what is the output logic sequence (truth table) of the two signals.
I believe that Circuit #2 sets all counter pin 2s and 3s high briefly to reset the counters
when the power is turned on, otherwise the output is low. Circuit #1 should do the
same thing but only when the time base cycle ends. So, I think that the truth table
should be

Code:
Circuit #1           Circuit #2           Pins 2 and 3
0                   0                    0
0                   1                    1
1                   0                    1
1                   1                    0            Shouldn't occur
Which would indicate that a 74LS00 NAND should be used.

Moderators note : used code tags to preserve spaces.

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#### djsfantasi

Joined Apr 11, 2010
7,187
I believe that Circuit #2 sets all counter pin 2s and 3s high briefly to reset the counters
when the power is turned on, otherwise the output is low. Circuit #1 should do the
same thing but only when the time base cycle ends. So, I think that the truth table
should be

Circuit #1 Circuit #2 Pins 2 and 3
0 0 0
0 1 1
1 0 1
1 1 0 Shouldn't occur

Which would indicate that a 74LS00 NAND should be used.
What’s the truth table of a NAND gate?

0 0 ?
0 1 ?
1 0 ?
1 1 ?

#### dl324

Joined Mar 30, 2015
12,207
I am concerned about a conflict since the output of both circuits will be connected to
pins 2 and 3 of each of the 74LS90 counters.
I missed the point that two circuits would be controlling the reset inputs. You need to use a gate to combine the two driving signals. Since no one else is telling you what gate to use, I'll leave that to you.

#### MrChips

Joined Oct 2, 2009
22,466
I believe that Circuit #2 sets all counter pin 2s and 3s high briefly to reset the counters
when the power is turned on, otherwise the output is low. Circuit #1 should do the
same thing but only when the time base cycle ends. So, I think that the truth table
should be

Circuit #1 Circuit #2 Pins 2 and 3
0 0 0
0 1 1
1 0 1
1 1 0 Shouldn't occur

Which would indicate that a 74LS00 NAND should be used.
What is the truth table for a 74LS00 NAND gate?
Does it match the truth table you have shown?

Joined Nov 25, 2020
68
I missed the point that two circuits would be controlling the reset inputs. You need to use a gate to combine the two driving signals. Since no one else is telling you what gate to use, I'll leave that to you.
I don't understand your last post Dennis.

Joined Nov 25, 2020
68
What is the truth table for a 74LS00 NAND gate?
Does it match the truth table you have shown?
It certainly matched the NAND truth table for the one I found on the internet. However, when I
looked in the TTL Cookbook I found that the one on the internet was wrong! Can't trust anything
on there. I see why you said that the OR gate is the one to use anyway. Thanks.

#### dl324

Joined Mar 30, 2015
12,207
I thought
I don't understand your last post Dennis.
I thought you were concerned about loading the output of the Schmitt inverter when what you were really concerned about was connecting two sub-circuits to the reset pins.
I see why you said that the OR gate is the one to use anyway.
What you wanted was to OR the reset signals so either could reset the counters without conflicting with the other. You could use a NAND, but then you'd have to invert all of the inputs.

EDIT:
However, when I looked in the TTL Cookbook I found that the one on the internet was wrong! Can't trust anything on there.
You can have more confidence when you get it from a place that's peer reviewed like AAC.

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#### MrChips

Joined Oct 2, 2009
22,466
There are different ways of solving this problem.

1) One way is to draw the truth table and see the results. You do have to pay attention when using negative logic.
What is negative logic?
Positive logic means that a logic HIGH (or 1) activates the desired function.
For example, if it is raining I will carry an umbrella.

Negative logic means that a logic LOW (or 0) activates the desired function.
For example, if it is not sunny I will carry an umbrella.
If it is raining I will not go to the beach.
If it is not sunny I will not play outside.

2) Another way is to think in positive logic.
If power-on reset is active OR counter limit is reached I want to reset the counter.

Then we apply bubble magic to the inputs or outputs if negative logic applies.
For example, if the inputs are inverted, we put bubbles on the input of the OR gate.
If the output is inverted, we put a bubble on the output.
Meanwhile the body of the gate remains an OR function regardless of what physical 74LSxx gate you end up using.

#### Audioguru again

Joined Oct 21, 2019
2,353
RS, you drew a Schmitt non-inverting buffer not a Schmitt inverter.
Why are you using 40 or 50 years old logic ICs? 40 years ago I got a Cmos Cookbook and never used old TTL again.

#### MrChips

Joined Oct 2, 2009
22,466
He also wrote 74LS14.

Joined Nov 25, 2020
68
There are different ways of solving this problem.

1) One way is to draw the truth table and see the results. You do have to pay attention when using negative logic.
What is negative logic?
Positive logic means that a logic HIGH (or 1) activates the desired function.
For example, if it is raining I will carry an umbrella.

Negative logic means that a logic LOW (or 0) activates the desired function.
For example, if it is not sunny I will carry an umbrella.
If it is raining I will not go to the beach.
If it is not sunny I will not play outside.

2) Another way is to think in positive logic.
If power-on reset is active OR counter limit is reached I want to reset the counter.

View attachment 224873

Then we apply bubble magic to the inputs or outputs if negative logic applies.
For example, if the inputs are inverted, we put bubbles on the input of the OR gate.
If the output is inverted, we put a bubble on the output.
Meanwhile the body of the gate remains an OR function regardless of what physical 74LSxx gate you end up using.

View attachment 224878
Thanks MrChips that was a very big help.
The counter works with five digits except for Circuit #1 (Gating Control). I have checked the wiring etc. But no dice.

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#### MrChips

Joined Oct 2, 2009
22,466
Please describe the function and theory of operation of your Circuit #1.

Joined Nov 25, 2020
68
Please describe the function and theory of operation of your Circuit #1.

View attachment 225024
Hi:

The circuit is supposed to change on the rising edge of each time base pulse.

When Latchout goes low, the latches should store the count. At the same time RST will be high
and the counter will be reset.

When Latchout goes high, the latch will just carry whatever value is on the data input. At the same time
RSTout will be low and the counter will resume counting.

Each time base pulse allows the input frequency to be counted and displayed.

At least this is what I think the original designer was trying to do.

RS

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#### MrChips

Joined Oct 2, 2009
22,466
Ah so. Then you did not design this circuit?
There are many things wrong with it.

Joined Nov 25, 2020
68
Ah so. Then you did not design this circuit?
There are many things wrong with it.
Hi:
since that explains why it doesn't work. How do I proceed?

RS

#### MrChips

Joined Oct 2, 2009
22,466
Firstly, I will point out two problems.

Someone replaced the original gates with 74LSxx series gates.
CD4000 series gates use CMOS technology.
74LS00 series gates use BJT technology.
They have very different characteristics and you cannot interchange the two without making adjustments.

PRE and CLR inputs on 74LS74 are active LOW. That is a dead give away why this circuit will never work.