Here is the circuit and resulting waveform now. The circuit needs to produce positive pulses on thehow about an 04 ?
does it matter if the 1Hz is inverted ?
I need two outputs. One with positive pulses on the rising edge of the time base and anotherwhat frequency are the pulses at, why do you need +ve and negative ?
I thought only positive were of interest ?
I am not sure that is what you want.I need two outputs. One with positive pulses on the rising edge of the time base and another
output with negative pulses on the falling edge of the time base.
That is what I am trying to do. The circuit that I have so far is just allowing me to see where the pulses are.I am not sure that is what you want.
If this is the design of a frequency counter then I would assume that you want:
1) a pulse to latch the data
2) a pulse to reset the counter
3) followed by a time interval based on your counting period
Ignore whether you need positive or negative pulses for now. That can be fixed later.
You need to draw a timing diagram to show the sequence of events that you want to occur.
Then you design the circuit to do this.
You know it is for a digital design and how can you say that the voltages are not correct?
That makes sense. How do I get that? The scope says that the square wave is 5 volts.
That makes good sense. Thanks.As to why +ve and negative pulses.
its a capacitor, voltage across a capacitor can not change instantaneously.
Start with assumption that output of capacitor is at zero,
rising edge on input to capacitor, 0 to 5 v ? what happens to the output of the capacitor ?
output of the capacitor follows input, then decays back to zero volts.
input changes 5v up, output of capacitor jumps to 5v, then decays
falling edge on input to capacitor, 5 to 0 v. output of capacitor was at 0v,
with input dropping 5v, the output of the capacitor must also drop 5v, then decay back to zero.
as capacitor output was at 0v, drop input 5v, output drops to -5v then decays back to 0v.
-5v into a logic gate , it wont last long.
You can stop the output of the capacitor going below 0 volts, with a diode,
how do you think you could connect a diode to the output of the capacitor to stop the output going below 0v ?
It seems to be working so far. The high logic signal is 3.2 V.Forrest Mimms and Don Lancaster are highly respected contributors to electronics. You can learn a lot by studying their publications such as TTL Cookbook by Don Lancaster. Rather than taking circuits wholesale out of their books you can further enhance your knowledge by studying each circuit and the properties and behaviour of each component.
The C-R circuit is a differentiator. The output is the derivative of the input.
View attachment 225263
As you can observe in the diagram and on your oscilloscope there is a positive going spike generated from the rising edge of the input signal. Similarly there is a negative going spike generated from the falling edge of the input signal.
If you want to apply this signal to the input of a digital logic gate you need to pay attention to the baseline voltage, i.e. the voltage at the flat portion of the signal.
A 7400 series or 74LS00 series digital gate expects a logic low input to be lower than 0.8V and a logic high signal to be higher than 2V. Does your waveform satisfy these requirements with a sufficient margin of error?
Your quest is to turn one of those two spikes (not both at the same time) into a digital pulse.
You can bias the baseline voltage towards GND with R connected towards GND as shown. In this manner the negative spikes goes below 0V and is not seen by the following gate.
Or you can bias the baseline voltage towards Vcc with R connected towards Vcc. The positive spike goes above Vcc and is not seen by the gate following.
Experiment with the values of C and R until you get the desirable result.
Note that 7400 and 74LS00 have different input characteristics and therefore will demand different values of R.
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