# Resolve Circuit Conflict #2

#### Hobbyist92

Joined Dec 17, 2020
25
so why do you need the divide by two then ?
what would the pulse you show look like if you just had a buffer in place of the divide by two ?
What should I use as a buffer?

#### andrewmm

Joined Feb 25, 2011
1,640
does it matter if the 1Hz is inverted ?

#### MrChips

Joined Oct 2, 2009
23,958
Treat any circuit off the internet as a reference point for your own design.

Do you know that the circuit works?
What is the purpose and operating conditions of each component?
What are the consequences of substituting a component with one with a different value or part number?

These are all valid questions and answer that will help to advance your knowledge, expertise and confidence.
Take the time to make personal progress one step at a time.

#### MrChips

Joined Oct 2, 2009
23,958

#### Hobbyist92

Joined Dec 17, 2020
25
does it matter if the 1Hz is inverted ?
Here is the circuit and resulting waveform now. The circuit needs to produce positive pulses on the
rising edge and negative pulses on the negative edge or vice versa, it doesn't matter just as long
as they are opposite.

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#### andrewmm

Joined Feb 25, 2011
1,640
what frequency are the pulses at, why do you need +ve and negative ?
I thought only positive were of interest ?

#### Hobbyist92

Joined Dec 17, 2020
25
what frequency are the pulses at, why do you need +ve and negative ?
I thought only positive were of interest ?
I need two outputs. One with positive pulses on the rising edge of the time base and another
output with negative pulses on the falling edge of the time base. I have attached a timing
diagram. The frequency will be 1 Hz.

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#### MrChips

Joined Oct 2, 2009
23,958
I need two outputs. One with positive pulses on the rising edge of the time base and another
output with negative pulses on the falling edge of the time base.
I am not sure that is what you want.

If this is the design of a frequency counter then I would assume that you want:

1) a pulse to latch the data
2) a pulse to reset the counter
3) followed by a time interval based on your counting period

Ignore whether you need positive or negative pulses for now. That can be fixed later.
You need to draw a timing diagram to show the sequence of events that you want to occur.
Then you design the circuit to do this.

#### Hobbyist92

Joined Dec 17, 2020
25
I am not sure that is what you want.

If this is the design of a frequency counter then I would assume that you want:

1) a pulse to latch the data
2) a pulse to reset the counter
3) followed by a time interval based on your counting period

Ignore whether you need positive or negative pulses for now. That can be fixed later.
You need to draw a timing diagram to show the sequence of events that you want to occur.
Then you design the circuit to do this.
That is what I am trying to do. The circuit that I have so far is just allowing me to see where the pulses are.
The rising edge pulse would latch the data and after a brief delay, the counter would be reset.
This would happen with each square wave. I don't understand why the pulses are alternating
positive then negative etc. Shouldn't they all be positive (or all negative)?

Desired timing diagram attached.

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#### MrChips

Joined Oct 2, 2009
23,958
You need to show the vertical scale, i.e. what are the voltages?

If this is for a digital design then the voltages don't meet the specifications of a digital signal.

#### Hobbyist92

Joined Dec 17, 2020
25
You need to show the vertical scale, i.e. what are the voltages?

If this is for a digital design then the voltages don't meet the specifications of a digital signal.

View attachment 225248
You know it is for a digital design and how can you say that the voltages are not correct?

#### MrChips

Joined Oct 2, 2009
23,958
You know it is for a digital design and how can you say that the voltages are not correct?
Because a line with a positive going spike and a negative going spike does not represent a digital signal to me.

#### MrChips

Joined Oct 2, 2009
23,958
As I said you do not have to worry about the polarity of the control signals. You can alter this later.

You need something like this:

#### Hobbyist92

Joined Dec 17, 2020
25
As I said you do not have to worry about the polarity of the control signals. You can alter this later.

You need something like this:
View attachment 225249
That makes sense. How do I get that? The scope says that the square wave is 5 volts.
I will also ignore the control signal polarity for now.

I modified the circuit by feeding the output into a 74LS04 to square it up. I have attached a new
schematic and scope image.

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#### andrewmm

Joined Feb 25, 2011
1,640
Why not register data on the rising edge, at the same time you clear the counter ?
then you only need one pulse ?

#### andrewmm

Joined Feb 25, 2011
1,640
As to why +ve and negative pulses.
its a capacitor, voltage across a capacitor can not change instantaneously.
rising edge on input to capacitor, 0 to 5 v ? what happens to the output of the capacitor ?
output of the capacitor follows input, then decays back to zero volts.
input changes 5v up, output of capacitor jumps to 5v, then decays

falling edge on input to capacitor, 5 to 0 v. output of capacitor was at 0v,
with input dropping 5v, the output of the capacitor must also drop 5v, then decay back to zero.
as capacitor output was at 0v, drop input 5v, output drops to -5v then decays back to 0v.

-5v into a logic gate , it wont last long.

You can stop the output of the capacitor going below 0 volts, with a diode,
how do you think you could connect a diode to the output of the capacitor to stop the output going below 0v ?

#### Hobbyist92

Joined Dec 17, 2020
25
As to why +ve and negative pulses.
its a capacitor, voltage across a capacitor can not change instantaneously.
rising edge on input to capacitor, 0 to 5 v ? what happens to the output of the capacitor ?
output of the capacitor follows input, then decays back to zero volts.
input changes 5v up, output of capacitor jumps to 5v, then decays

falling edge on input to capacitor, 5 to 0 v. output of capacitor was at 0v,
with input dropping 5v, the output of the capacitor must also drop 5v, then decay back to zero.
as capacitor output was at 0v, drop input 5v, output drops to -5v then decays back to 0v.

-5v into a logic gate , it wont last long.

You can stop the output of the capacitor going below 0 volts, with a diode,
how do you think you could connect a diode to the output of the capacitor to stop the output going below 0v ?
That makes good sense. Thanks.

Are you saying that the output would not have to be routed through an inverter if I used a diode?

I disconnected the inverter on the output and placed a diode across the capacitor with the cathode connected
to the end that is connected to the first inverter. That changed the circuit output to a square wave with the
same pulse width as the time base, rather than a positive pulse.

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#### MrChips

Joined Oct 2, 2009
23,958
Forrest Mimms and Don Lancaster are highly respected contributors to electronics. You can learn a lot by studying their publications such as TTL Cookbook by Don Lancaster. Rather than taking circuits wholesale out of their books you can further enhance your knowledge by studying each circuit and the properties and behaviour of each component.

The C-R circuit is a differentiator. The output is the derivative of the input.

Reference: https://www.electronics-tutorials.ws/rc/rc-differentiator.html

As you can observe in the diagram and on your oscilloscope there is a positive going spike generated from the rising edge of the input signal. Similarly there is a negative going spike generated from the falling edge of the input signal.

If you want to apply this signal to the input of a digital logic gate you need to pay attention to the baseline voltage, i.e. the voltage at the flat portion of the signal.

A 7400 series or 74LS00 series digital gate expects a logic low input to be lower than 0.8V and a logic high signal to be higher than 2V. Does your waveform satisfy these requirements with a sufficient margin of error?

Your quest is to turn one of those two spikes (not both at the same time) into a digital pulse.

You can bias the baseline voltage towards GND with R connected towards GND as shown. In this manner the negative spikes goes below 0V and is not seen by the following gate.

Or you can bias the baseline voltage towards Vcc with R connected towards Vcc. The positive spike goes above Vcc and is not seen by the gate following.

Experiment with the values of C and R until you get the desirable result.

Note that 7400 and 74LS00 have different input characteristics and therefore will demand different values of R.

#### MrChips

Joined Oct 2, 2009
23,958
Another solution is to use a 74LS123 dual monostable multivibrator and from this chip you will be able to generate both the LATCH and RESET signals that you need (in both polarity flavours).

#### Hobbyist92

Joined Dec 17, 2020
25
Forrest Mimms and Don Lancaster are highly respected contributors to electronics. You can learn a lot by studying their publications such as TTL Cookbook by Don Lancaster. Rather than taking circuits wholesale out of their books you can further enhance your knowledge by studying each circuit and the properties and behaviour of each component.

The C-R circuit is a differentiator. The output is the derivative of the input.

View attachment 225263

Reference: https://www.electronics-tutorials.ws/rc/rc-differentiator.html

As you can observe in the diagram and on your oscilloscope there is a positive going spike generated from the rising edge of the input signal. Similarly there is a negative going spike generated from the falling edge of the input signal.

If you want to apply this signal to the input of a digital logic gate you need to pay attention to the baseline voltage, i.e. the voltage at the flat portion of the signal.

A 7400 series or 74LS00 series digital gate expects a logic low input to be lower than 0.8V and a logic high signal to be higher than 2V. Does your waveform satisfy these requirements with a sufficient margin of error?

Your quest is to turn one of those two spikes (not both at the same time) into a digital pulse.

You can bias the baseline voltage towards GND with R connected towards GND as shown. In this manner the negative spikes goes below 0V and is not seen by the following gate.

Or you can bias the baseline voltage towards Vcc with R connected towards Vcc. The positive spike goes above Vcc and is not seen by the gate following.

Experiment with the values of C and R until you get the desirable result.

Note that 7400 and 74LS00 have different input characteristics and therefore will demand different values of R.
It seems to be working so far. The high logic signal is 3.2 V.

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