Have a look at this
http://www.nutsvolts.com/magazine/article/transistor_clock

View attachment 126552

Hmmmmm..... Well I browsed it and I bookmarked the home website. Looks a good one for hobbyists. Thankyou.

But seriously, all I want to do is build ONE single-output oscillator. Ideas?

 

1Those are not rectifiers. Those are inverters. A simple logic gate actually is a very high gain linear amplifier acting as a comparator.
..........
2To learn more with less work, consider building it using sections of a hex inverter or quad NAND gate. Since you don't need a reset pin and are not driving other loads, you need only two inverters to reproduce this oscillator.
.................
3 Suffice to say that you should use gates with hysteresis, such as the CD4093 or CD40106.

https://en.wikipedia.org/wiki/Hysteresis (after the basics, skip down to "electronic circuits")

https://en.wikipedia.org/wiki/Schmitt_trigger

ak

1 yep I meant inverters
2 pt taken
3 ok sounds good. I wld like to make that the next project - before nuancing the irritation circuit in the manner suggested by dendad and you eg adding a 555 to vary individual relay times - which I still intend to do. But after I learn more abt basic logic gates.

I'll buy some 4093s / 40106s and get to.

I googled it and there's lots of practical literiture for me to draw on .. + u guys!

Eg this relic from antiquity: https://forum.allaboutcircuits.com/...9/?temp_hash=bea0a16322b411504716dbb256816c4a

 

1 yep I meant inverters
2 pt taken
3 ok sounds good. I wld like to make that the next project - before nuancing the irritation circuit in the manner suggested by dendad and you eg adding a 555 to vary individual relay times - which I still intend to do. But after I learn more abt basic logic gates.

I'll buy some 4093s / 40106s and get to.

I googled it and there's lots of practical literiture for me to draw on .. + u guys!

Eg this relic from antiquity: https://forum.allaboutcircuits.com/...9/?temp_hash=bea0a16322b411504716dbb256816c4a

Mellisa, I strongly suggest you download digital works. It's an excellent way to learn about digital gates and logic, and it's very easy to use. Plus it's free!

 

Mellisa, I strongly suggest you download digital works. It's an excellent way to learn about digital gates and logic, and it's very easy to use. Plus it's free!

Ok thx for the advice cmartinez. I will! I'll let I know how I go
Mellisa

 

I googled it and there's lots of practical literiture for me to draw on .. + u guys!
Eg this relic from antiquity: https://forum.allaboutcircuits.com/...9/?temp_hash=bea0a16322b411504716dbb256816c4a

Excellent article; I still have the original. Note that the oscillator that is the basis for most of the circuits is not the same as the oscillator in the 4060. That one is based on two gates in series, and only the one between pins 11 and 10 would benefit by having hysteresis. Note that the datasheet does not indicate this, although the "2.2" factor in the equation is a strong indication that it is in there. More reading is attached.

ak

 

1 yep I meant inverters
2 pt taken
3 ok sounds good. I wld like to make that the next project - before nuancing the irritation circuit in the manner suggested by dendad and you eg adding a 555 to vary individual relay times - which I still intend to do. But after I learn more abt basic logic gates.

I'll buy some 4093s / 40106s and get to.

I googled it and there's lots of practical literiture for me to draw on .. + u guys!

Eg this relic from antiquity: https://forum.allaboutcircuits.com/...9/?temp_hash=bea0a16322b411504716dbb256816c4a

Nice article, but there's an error in Figure 2 B in that the first pulse is shown as being the same width as the subsequent pulses.

Since, for the first pulse, the capacitor has to charge to Vp from Vee before the output changes state, it'll take longer than the subsequent pulses, which will switch between Vp and Vn, like this:

 

Nice article, but there's an error in Figure 2 B in that the first pulse is shown as being the same width as the subsequent pulses.

Is that significant?

 

Depends on the application. This is a common "feature" of all relaxation oscillators and many other oscillator types. In your case it is 1/32768th of the first timing cycle. I doubt the plants will notice.

ak

 

Depends on the application. This is a common "feature" of all relaxation oscillators and many other oscillator types. In your case it is 1/32768th of the first timing cycle. I doubt the plants will notice.

ak

kewl

 

Is that significant?

Might or might not be, but it's just intended as a heads-up.

 

Might or might not be, but it's just intended as a heads-up.

Thankyou for your consideration, E.

Regards

Mellisa

 

download digital works. It's an excellent way to learn about digital gates and logic, and it's very easy to use. Plus it's free!

Hi @cmartinez
Just letting you know I have just downloaded Digital Works and the Firefly compiler. Its on my list to look at. There is so much to learn! I am feeling overwhelmed but will battle on.
M

 

I'm not a big fan of large R-C timers, but in this case precision is not required. Here is a first pass at the idea. Note that C1 might have to be increased if its leakage current is a noticeable percentage of the charging current.

http://www.ohmslawcalculator.com/555-astable-calculator

ak
View attachment 126056

hello @dendad hello @AnalogKid

You guys developed some circuit ideas to expand the irrigation timer project in Post #122, #125 and #131.

This is to just let you know I haven't started work on it yet. But that I do intend to do so as soon as I get a chance.

I'm currently spending my electronics hobby time consolidating my learning about oscillators and counters from the irrigation timer circuit by delving into logic gates with a program suggested by @cmartinez in Post #163. I also have lots of oscillator circuits to read as suggested by @Wendy in one of her AAC articles at: https://forum.allaboutcircuits.com/threads/leds-555s-flashers-and-light-chasers.19075/

I am sooooo glad I chose this sub field of electronics as my first introduction to the broader hobby. I am enjoying it immensely. And its got lots of applications to solve things in my life that I didn't realise existed!!

For example, I am researching proximity capacitance switching sensor plates. (See attached paper from Fujitsu.) This might be my next project. I would like to improve my disabled uncle's quality of life. A brain aquired injury left my uncle with palsy and cognitive impairments including speech and learning difficulties. Many years ago a car accident smeared away part of his prefontal cortex. All the switches in his life have mechanisms in them that require motor skills to operate that my uncle simply does not possess. He can make a switch work on his own but only with disproportionate difficulty and perserverance. Its an exhausting struggle, occupying a large amount of his attention, time and effort. I dont think it needs to be so difficult for him to turn his things on and off.

A sensor plate like the ones described here might be feasible for me to make for him in this youtube video:

This author has published a written report, attached, based on his youtube video. At this stage, I am only gathering resources on the internet. When I think I know enough to have an intelligent conversation about this type of switch with you and your AAC colleagues, I will post a new thread. Happening soon!!!

Thanks again for all your help (including the others mentioned above and also other helpers on the irrigation project eg @#12 @GopherT @KeepItSimpleStupid @EM Fields +more)

Mellisa

 

Back to post #105.The ULN2003 is a bad chip for newbies to understand.

Pin 10 of ULN2003 stays stuck on 4.8VDC. Will not advance. There is about 1V on the other six output pins. Placement of shunt at P1 makes no difference eve

I think the datasheet has a common (COM) and ground, No + power. An wouln't you know COM generaly goes to a + voltage, buy it's not needed unless driving relays. So for understanding erase all of the diodes and the COM connection.

What your left with are transistors with different base configurations for the ULN200x chips that adapt to various logic families. That said, they exist as open collector drivers where no + is needed for the chip to function, just base current.

Since relays that are driven by transistors need a diode clamp. The inductor stores the voltage because the inductor's current can't change instantaneously briefly when turned off. of the relay coil.

When you put those diodes in place, each output gets he cathode of the diode and the anode goes to the relay supply voltage.

The nice thing about the ULN200x chips is that with the inputs disconnected, the device is OFF. TTL inputs float high when not connected and many processor ports default to an input or high Z state when initially turned on, so the things your trying to control are off at power up until they are correctly configured for an output with a 0 state.

True CMOS inputs should never float. Rule is to make the unused gates use the least amount of power when selecting a 0 or 1 as the input.

There is an 8 channel version of this chip. You have to watch the total power dissipation.

 

Back to post #105.The ULN2003 is a bad chip for newbies to understand.



I think the datasheet has a common (COM) and ground, No + power. An wouln't you know COM generaly goes to a + voltage, buy it's not needed unless driving relays. So for understanding erase all of the diodes and the COM connection.

What your left with are transistors with different base configurations for the ULN200x chips that adapt to various logic families. That said, they exist as open collector drivers where no + is needed for the chip to function, just base current.

Since relays that are driven by transistors need a diode clamp. The inductor stores the voltage because the inductor's current can't change instantaneously briefly when turned off. of the relay coil.

When you put those diodes in place, each output gets he cathode of the diode and the anode goes to the relay supply voltage.

The nice thing about the ULN200x chips is that with the inputs disconnected, the device is OFF. TTL inputs float high when not connected and many processor ports default to an input or high Z state when initially turned on, so the things your trying to control are off at power up until they are correctly configured for an output with a 0 state.

True CMOS inputs should never float. Rule is to make the unused gates use the least amount of power when selecting a 0 or 1 as the input.

There is an 8 channel version of this chip. You have to watch the total power dissipation.

Thanks for your post @KeepItSimpleStupid

That issue was resolved a while ago. It was a problem caused by my inexperience working with the bread board from memory. User error. Its working really well now.

Nevertheless, you've made some useful comments about the chip I can still benefit from though for next time.

Thanks again for your interest

Mellisa

 

I am sooooo glad I chose this sub field of electronics as my first introduction to the broader hobby. I am enjoying it immensely. And its got lots of applications to solve things in my life that I didn't realize existed!!

I'm glad this is turning into an education instead of an intimidation. I think I see you are back to digital gates and counters instead of microprocessors. As an old hand at this, and also a bit too old to prefer MPUs, I thought this was a piece of cake on the first page. Now you're at 175 posts? Whew! It really turned into an education! That's good. Most people come here because they don't want to learn. They want the circuit handed to them.

Congratulations. You have at least a thousand excellent days ahead of you!

 

Depends on the application. This is a common "feature" of all relaxation oscillators and many other oscillator types. In your case it is 1/32768th of the first timing cycle. I doubt the plants will notice.

ak

No offense intended, but "I doubt the plants will notice" sounds to me like snark.
It isn't really a question of the plants noticing since we all know they have a pretty long time constant, it's just a critique of Braga's probably accidental misrepresentation of reality and setting the record straight.

 

Yes. And, I'm stupid. I've been using P0 and P1 for this part for decades, and completely forgot about the Phi marking.

P1, P0-, and P0 are the inputs and outputs of two inverters in series, so the states of those pins always are 1-0-1 or 0-1-0. We'll call the inverters Left and Right.

Start at the moment P0 goes high.

The voltage across a capacitor cannot change instantaneously, so this pulls the timing node (Rx-Cx-Rs) high. This puts a high at P1 (the Left input). It tries to put a high at P0- through Rx, but P0- is held low by the Left output.

This operating state is stable, because two inverters in series forms a latch due to positive feecback: P0 is high, P1 is high, P0- is low, P0 is high.

But while this state is stable, there is a voltage across Rx because the left end of Cx is high but P0- is low. So Cx discharges through Rx into the P0- low output of the Left inverter.

After a time, the voltage at the Rx-Cx-Rx node is low enough that Left input P1 sees it as a logical low, and Left changes state.

P1 is low, P0- goes high, P0 goes low.

Now everything is reversed from where we started, and Cx starts charging in the opposite direction.

Describing an oscillator in text always is difficult, so try to digest this and ask away.

ak

Describing an oscillator in text always is difficult, so try to digest this and ask away.

thanks for the invite AK so here goes.. (I am revisiting this bit about the oscillator circuitry of the 4060)..
1) when you talk of the "oscillator node" do you mean, collectively, the external circuitry inside the dotted lines in Figure 1, below?:

Figure 1

2) your shorthand for the oscillator node is also "Rx-Cx-Rs", yes? Figure 3 below is taken from a datasheet and it shows this.
3) Again by convention, how does the subscripting x and s makes sense to this?
4) Looking at the Phi marking convention (see Figure 2, below):
-- 4a) Phi0 and Ph0- are output1 and output2, (or left and right, or pin9, pin10) respectively in your narrative above, yes?
-- 4b) Your narrative talks about input left and input right. its clear that input left is pin 12 (denoted Phi1 which is also sometimes called the Clock pin), yes?
-- 4c) your narrative only implies the existence of the left input. This would be the RESET pin 12 would it? this needs to be earthed (low) for the oscillator to operate

Figure 2

6) Concerning the inverter gate logic in your post:
-- 6a) Some logic diagrams of the oscillator built into the 4060 depict the gates using only the NOT gate symbol. Others show a NAND gate in place of the NOT gates between pins 11 (clock) and 12 (reset) Figure 2 above does this while Figure 3 below shows the same thing with just NOT gates:

Figure 3

My question in (6a) then is what does a NAND gate drawn with just NOT gates actually look like? Can you perhaps point me to a link which shows this?
-- 6(b) Last question, is it possible to restate your narrative in your post above using the conventional truth tables of the NOT and the NAND gates? If I could see just an example of this I think that would be helpful since I seem to be able to work with the truth table format and that is what I want to practice on as I explore the world of gate logic.

 

1. Almost. The "timing node" or "Rx-Cx-Rs node" (there is a typo in my original post) is the point in Figure 1 where (R1+R2), C1, and R3, or the point in figure 3 where Rx, Cx, and Rs are connected. There is a modified sawtooth wave at this node, and that is the heart of how this circuit works. It takes time for the voltage on the capacitor to wander up and down between approx. 1/3 and 2/3 Vdd. That time, set by the Rx and Cx values, sets the oscillator frequency.

Rs is not supposed to affect the Rx-Cx timing relationship. CMOS gates have protection diodes on the input to protect them from external transients. Those diodes can distort the timing sawtooth, affecting the accuracy of the timing equation. By isolating the diodes with a large resistor, that distortion is reduced. Rs should be at least 10 times Rx.

2. Yes.

3. Calling out external timing components with alphabetic subscripts goes way back. TI called the 74121 monostable timing components Rt and Ct. This is because the components are mandatory for the circuit to work, but of course the manufacturer does not know where they fit in on the bill of materials for the user's design. So in a final design they might be R12 and C73.

4. Yes, yes, not sure what you mean. I don't mention the Reset input. Clearly, it must be in the non-reset state for the circuit to work.

5. - - -

6a. In figure 3, the second inverter after pin 12 enters the side of the inverter at pin 11. This is one way of showing an enable function. Pin 12 enables or disables pin 11. This visual is common in devices with tri-state output stages like octal latches:


Th effect is the same as a NAND or AND gate.

6b. The R-C time delay does not translate well into a truth table.

ak

 

Way back somewhere in this thread you said:

e can make a switch work on his own but only with disproportionate difficulty and perserverance. Its an exhausting struggle, occupying a large amount of his attention, time and effort. I dont think it needs to be so difficult for him to turn his things on and off.

Our local hospital has a lot of "wave here" type of switches for door openers.

e.g. Look at the Next Gen switches here: http://www.disabilitysystems.com/door-controls/handicap-door-activation.html

Reneasys (sp?) has a lot of uP based cap sensor stuff.

Take a look here https://www.itead.cc/itead-touch-network-intelligent-switch.html as well. They had some basic breadboard cap switches somewhere on their website at one time. I don;t have time to look right now. This one is unique.