Hi,
I have a confusion about sampling time and conversion time. In STM32F407, the conversion time for 12 bit resolution of ADC is 12 clock cycles. But there is an option to set the sampling rate at 3 clock cycles. Hence, every three clock cycles, a sample will be taken. But I will have to wait for 12+3=15 clock cycles to assign the converted value to a variable. What will happen to the ADC samples in between this period? Are they lost?

 

13.5 Channel-wise programmable sampling timeThe ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12 cycles
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
Tconv = 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz

The ADC samples, and then the sampler goes into hold mode and the converter
starts its SAR algorithm. So during conversion time the sampler is effectively disabled.

How a SAR works - https://www.silabs.com/community/mc...ntry.html/2004/02/11/sar_successive_appr-dRNn

The sampler, by your design, should settle in its configed time, to 1/2 LSB
of 12 bits, if thats the accuracy you are seeking. Roughly speaking.

Regards, Dana.

 

Sample time of 3 clock cycles is an internal operation of the ADC system.
The fastest conversion time is still 3 + 12 = 15 cycles
With ADCCLK = 30MHz
Tconv = 15 x 1/30MHz = 0.5μs
Maximum sampling rate is 2Msps if you use DMA.
Sampling rate will be lower if you use programmed I/O.

 

So 3 cycles is the duration of time over which over which sample is taken and after the duration, conversion takes place for another 12 cycles and only after that conversion will samples be taken again for 3 cycles?

 

Yes.

Some architectures allow termination of sampling and/or conversion cycle,
but then that whole time period becomes useless.

In general 15 clocks, unless you mod the sampling time, is the total.

Regards,Dana

 

Yes.

Some architectures allow termination of sampling and/or conversion cycle,
but then that whole time period becomes useless.

In general 15 clocks, unless you mod the sampling time, is the total.

Regards,Dana

Suppose my PCLK is 42 Mhz and I am using a clock source of PCLK/4 for my ADC which is 10.5Mhz, then the time period is 1/10.5Mhz =9.52 x 10^-8 seconds. I am using 480 cycles as sample time and it takes 12 clock cycles for conversion which accounts for a total of 492 clock cycles.
Then will the sampling duration be 492 x 9.52 x 10^-8 = 46.8 microseconds?
And suppose I have an input signal of 100 ms, then will I get 100ms/46.8us= 2136 samples?

 

For your last post try it out.

On another matter if using interrupts that will produce jitter
in sample retrieval (in time domain). Unless a DMA process
with no buss contention.

If you use interrupts minimize f() calls and processing inside
ISR as that causes a lot of stack push, latency, etc..

Just set a flag, exit, then process.

Regards, Dana.

 

For your last post try it out.

On another matter if using interrupts that will produce jitter
in sample retrieval (in time domain). Unless a DMA process
with no buss contention.

If you use interrupts minimize f() calls and processing inside
ISR as that causes a lot of stack push, latency, etc..

Just set a flag, exit, then process.

Regards, Dana.

Okay. I think I am correct, on comparison with @MrChips answer.