I can imagine such a thing, but it would take a fairly complicated bit of circuitry inside an FPGA. Using a very high frequency clock I would sample the incoming signal and use the duty cycle ratios with a slower clock to produce the output signal. I'm guessing this would not be practical for your application.View attachment 281639
Dear all, may I ask if there is a circuit which output a reduced-frequency of square waveform given in its input while maintaining its duty cycle?
Thank you for reading
Well, I guess it would need some sort of memory I believe. Because if the duty cycle is different for different times, it would require some sort of memory to store it so that after processing, it will produce a sqaure wave with a lower frequencyI think you would need a microprocessor to do that.
Of course.Well, I guess it would need some sort of memory I believe
What is generating the PWM signal? If it is a microcontroller, you can simply add a slower crystal (if it uses a slower external crystal). Since PWM is a register of frequency ticks and a second register for clock ticks on state.Well, I guess it would need some sort of memory I believe. Because if the duty cycle is different for different times, it would require some sort of memory to store it so that after processing, it will produce a sqaure wave with a lower frequency![]()
As is often the case, SO much important information is left out?View attachment 281639
Dear all, may I ask if there is a circuit which output a reduced-frequency of square waveform given in its input while maintaining its duty cycle?
Thank you for reading
Would have to give it a little more thought but I'm thinking a 2 input AND gate along with a Dual D Flip Flop. But the logic behind that might not work. Have a lot to get to today so it'll be quite a while before I get back here.View attachment 281653
Dear all, may I ask if there is a circuit that produces the following input and output which basically reduces its frequency by 2 times which also basically stretch out the input waveform to produce the following output?
Thank you for reading![]()
Hi, take your timeWould have to give it a little more thought but I'm thinking a 2 input AND gate along with a Dual D Flip Flop. But the logic behind that might not work. Have a lot to get to today so it'll be quite a while before I get back here.
Yes, thats rightAm I missing something? What I see in the example is a transition at time t in the input comes at time 2t get in the output.
So, after 100 second the, the output is putting out the one seen at 50 seconds in the input.
So the input needs to be stored in some fashion
with the storage needed continuing to increase the longer it runs.
Yes. The input pulse and timestep are just examples. Sure, the height of pulses can change as you like it. But the function of reducing the frequency by halved must be achievedOkay, so how long does it have to run?
And, with what time resolution.
And can the height of the pulses vary? Do we have to duplicate that? With what resolution?
Or, better still, what problem are you trying to solve?
Well, erm maybe just take 1 seconds of inputs, and you know store it perhaps, and output 2 seconds of outputs. I believe this is extremely easy when we use microcontroller so that's I am curious to do this in analog manner for learning processSo if this system has been running for two days. the output is is the extended pulses from a day ago, right?
Do you not see a problem with that?
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