For the 8 bit computer I am building, I was supposed to get 74LS189, but that was impossible to find, so I read I could sub it with an HM6116-LP4 block.

The thing is, I can't find a decent datasheet on how this works, and I can't find articles where other people have fiddled (upon writhing this, I did, but I'd rather give this a go myself at first) with this chip. I have never worked with memory before, so I know very little about this, other than what I've read today.

How do I use the row- and column decoder?

It's a 2048-word x 8 bit chip. To access all these words, I need 11 address pins, right? 2^11 gives 2048, which corresponds with the A0 to A10 pins. And each word is 8 bits long, aey?

Does this mean this chip is a "perfect" fit for an 11 bit computer? Mine is 8 bits, so I can access 256 words of these 2048, If my logic is correct.

When I write in C (I try...) "int StrongPengin = 4;", does this number 4 then occupy an entire row (can I say word?) and an address with it? The variable name StrongPenguin, does this also get it's word spaces? I am assuming this would take up quite a few rows. Does the computer store it is chronological order, like I did in my drawing, or is it just random? Please see the second attachment.

I made some Paint drawings, trying to brush up the sloppy datasheets I found.

 

For the 8 bit computer I am building, I was supposed to get 74LS189, but that was impossible to find, so I read I could sub it with an HM6116-LP4 block.

74189 might be an easier substitution. Jameco has several hundred in stock.

At least 6116 are TTL compatible, so you only need to worry about timings.

How do I use the row- and column decoder?

You don't need to be concerned about it. The chip will do the decoding for you. You just supply an address.

It's a 2048-word x 8 bit chip. To access all these words, I need 11 address pins, right? 2^11 gives 2048, which corresponds with the A0 to A10 pins. And each word is 8 bits long, aey?

For longer "words", you just use more byte wide chips.

When I write in C (I try...) "int StrongPengin = 4;", does this number 4 then occupy an entire row (can I say word?) and an address with it? The variable name StrongPenguin, does this also get it's word spaces?

It depends. Words are usually 16 bits, but it can be more or less.

Does the computer store it is chronological order, like I did in my drawing, or is it just random?

It depends on the compiler, but variables are normally stored close to each other with some optimization for alignment.

 

74189 might be an easier substitution. Jameco has several hundred in stock.

At least 6116 are TTL compatible, so you only need to worry about timings.
You don't need to be concerned about it. The chip will do the decoding for you. You just supply an address.
For longer "words", you just use more byte wide chips.
It depends. Words are usually 16 bits, but it can be more or less.
It depends on the compiler, but variables are normally stored close to each other with some optimization for alignment.

I might just buy a 74189, but I think I will try to see this challenge through. Everything is possible with a little help from the fine citizen of AAC.

It was just the column decoder that threw me off, as the 189 chip doesn't have that, only a row. And I thought addresses only were in rows.

Can I just ignore the column decoder, and just use the row? Or have I misunderstood something?

My computer has 8 bits, and this chip uses 11 to get access to all the ram bits, and the row decoder uses 8 bits (I might be mixing pins and bits..) to access rows.

 

As @dl324 said, you do not have to worry about row and column addressing. This is internal to the chip.

74189 is 64-bit read-write memory, organized as 16-words of 4 bits. You will need 32 of these to implement a 256-byte memory.

The other thing you need to consider is the access time required by your system.
HM6116LP-4 access time, address to data is 200ns.
74189 is about 10 times faster with access time around 20ns.

 

It was just the column decoder that threw me off, as the 189 chip doesn't have that, only a row. And I thought addresses only were in rows.

The HM6116 uses a 128x128 array, so they needed decoders to make it appear to be a 2Kx8 array. That was a common practice for memory arrays which placed the memory bits in 1 or 2 arrays so they could put the I/O's around the perimeter.

Back in those days, they only used 2 layers of metal and it made routing easier. These days, they have a dozen metal layers and don't use wire bonding so they can route over the array and put the I/O's anywhere (within constraints) because they use IBM's C4 bump methodology.

 

@MrChips Ok, I will try not worry about it. The original design uses two 74LS189 chips, total 32 words. Mine has 2048, so I should be well covered.

About the timing. This seems a bit tricky, since the 74LS245 tri-state buffer works in the 15 to 30 ns range, while HM6116 is at 200 ns. I'm guessing it's doable, since I read two examples, but none of them showed the timing circuit part, just connecting of the ram block. Would I have to make a separate clock for this job?

@dl324 Ok, so it sounds like a convenience kind of thing. So I can just ignore the column selector part, and just use the row decoder (Pin A1 to A7)? Doing it this way, the chip becomes a 128 word block, right? 2^7 = 128. My computer only has 4 address lines, so it doesn't matter.

Do modern day PC's still use column decoders? I keep asking about this row/column business, because it's just so much easier to imagine a long row of memory words each it's own address, than a matrix.

 

@MrChipsAbout the timing. This seems a bit tricky, since the 74LS245 tri-state buffer works in the 15 to 30 ns range, while HM6116 is at 200 ns. I'm guessing it's doable, since I read two examples, but none of them showed the timing circuit part, just connecting of the ram block. Would I have to make a separate clock for this job?

It's not that simple. When memory is slower than the "CPU" frequency, wait states need to be built in to account for memory being slower.

So I can just ignore the column selector part, and just use the row decoder (Pin A1 to A7)? Doing it this way, the chip becomes a 128 word block, right? 2^7 = 128. My computer only has 4 address lines, so it doesn't matter.

You have no choice, you can't access the bits directly.

Do modern day PC's still use column decoders? I keep asking about this row/column business, because it's just so much easier to imagine a long row of memory words each it's own address, than a matrix.

Many different schemes are used to build memory modules. Most/all of them try to hide implementation details.

 

It's not that simple. When memory is slower than the "CPU" frequency, wait states need to be built in to account for memory being slower.
You have no choice, you can't access the bits directly.
Many different schemes are used to build memory modules. Most/all of them try to hide implementation details.

Ok, that sounds a bit difficult. I will have to think about if I wanna get into this mess.
Sweet, that settles that, then.

I read many places about these memory arrays. Is it just a specific set of addresses (say like a 100 addr.) with specific content? So when I see "array 4", that would contain a set of certain addresses and "array 5" another set. Is the correct understood?

 

I read many places about these memory arrays. Is it just a specific set of addresses (say like a 100 addr.) with specific content? So when I see "array 4", that would contain a set of certain addresses and "array 5" another set. Is the correct understood?

You don't need to worry about physical addresses unless you're programming in assembly language. In higher level languages, the compiler hides absolute addresses.

That being said, there are times when you'll need to know the actual address of certain data. For example, I'm learning how to use the GPIO in ARM processors. There's a sysfs interface (that uses the file subsystem) to access them. On the processor I'm using, the highest frequency I can get from 1 I/O using sysfs is around 150kHz. If I use the register interface, I can map a portion of memory into my program and write to specific addresses in memory to toggle the I/O's. I found that I can toggle one or more I/O's in the same word at 5MHz.

 

@dl324 Ok, the compiler hides that. I was mostly just trying to understand the whole array thing, when reading about coding, trying to visualize the array.

That sounds very interesting, and cool. Is it some sort of hack?

 

Ok, the compiler hides that. I was mostly just trying to understand the whole array thing, when reading about coding, trying to visualize the array.

This is the block diagram for a 256Kb EPROM:

The actual bit cell matrix was broken into two arrays that you can see in any 256Kb EPROM (AMD 27C256). I first became aware of that when I worked at a company that made EPROMs. There was a 64Kb CMOS design that was drawn in a way that it could be easily expanded to 256Kb. I'll see if I have any die photos to illustrate.

That sounds very interesting, and cool. Is it some sort of hack?

The addresses for the registers are documented in the user manual. On ARM processors, it's called bit banding; though I think some refer to it, incorrectly, as bit banging.

 

Die photos of 3 generations of Intel EPROM (64Kb, 128Kb, and 256Kb):

From 1991 Memory Products databook.

 

@dl324 That's a good block diagram, much better than the one I found for my HM6116. I will just accept the decoding part and not worry.

Btw; next on my menu is to decipher the voltage reg circuit you came with. I haven't really had time to do it yet. I will post an update in that thread, see if I get it right.

Thanks for all the help. Much appreciated.

 

That's a good block diagram, much better than the one I found for my HM6116. I will just accept the decoding part and not worry.

Just occurred that the die photos I posted needed some explanation.

I boxed 64Kb in green and 128Kb in red in the following die photo of a 256Kb EPROM. You can compare the boxed regions with the photos posted previously.

They typically changed process between generations, but I worked with some people who designed those parts and knew what their method was. They knew they were going to be doubling capacity, so they planned the layout to make subsequent parts less work.

They were just starting to use CAD back then. Before that, they drew (using straight edges and colored pencils) on mylar graph paper. That was then "digitized" into a Calma graphics system. Before that, they cut "ruby" to make the masks. The process was quite labor intensive.

I was a systems manager for one of the first interactive graphics systems (Applicon) where the polygons were entered directly. The "draftsmen" became computer operators and replaced pencils/rulers with a computer stylus, and "digitizing" started down the path of becoming an obsolete job.

Btw; next on my menu is to decipher the voltage reg circuit you came with. I haven't really had time to do it yet. I will post an update in that thread, see if I get it right.

Take your time.

 

@dl324 Very interesting getting some background/history on these blocks. It's just nuts to think about what they did with pen and paper.

I don't have much to add, or any good questions, since this is a few levels above my knowledge