PWM-FET driving optimum timer / pulse speed?

Thread Starter

pmd34

Joined Feb 22, 2014
503
I am playing with a project for making a sine wave inverter for low voltage. There is a very good TI paper talking about a reference design here:
http://www.ti.com/lit/an/slaa602a/slaa602a.pdf

However I dont really need to confine myself to 50Hz. So I thought it would be interesting to get to grips with some CPLD programming and VHDL so potentially allow much quicker speeds than with a microcontroller and lookup table.

Doing all the number crunching for the number of Duty cycle modulated pulses, ultimate clock speed (that makes up these pulses).. etc. it works out at a very great number of clock pulses. Ideally the resulting sine wave should be beyond audio frequency so there is no annoying buzzing, but I guess if you get much beyond 1uS on / off time (?) for the FETs your starting to get significant switching losses while the FET is actually trying to switch state.

So... any hard and fast guidelines for a good ball park minimum off / on time for your average power mosfet? Or other things Ive undoubtedly forgotten?!
 

Papabravo

Joined Feb 24, 2006
12,767
To get some idea of what you are up against, look on the FET datasheet for an item called the "gate charge" in units of coulombs. This is the charge required to turn the FET on and off. The way you supply or remove charge rapidly is with a current source and a current sink. There are also secondary effects of inter-electrode capacitance, but this is the big one. See what you think it will take to switch a FET at 1MHz.
 

Thread Starter

pmd34

Joined Feb 22, 2014
503
Im really just "playing" with the technology at the moment, so I figure something around 2A at 60V ish.. that way there are plenty of FETs that can cope with the voltage, and the current is not so large that I have to worry too much.
 
Top