I would not commit to a pc board yet. The circuit needs decoupling capacitors, attention to other unused pins, etc. Also, I would prototype it first to make sure the timing is correct for your application. You must use a scope to verify the output waveform.

ak

 

I changed again and attached it.
I am wondering if this logic is good to be implemented on the PCB, or there still needs to add some components like resistors and capacitors to the logic to protect the circuit and for its practical use.
Thank you again

dj

Hi

Would you like a copy of the EL7104 to complete your simulation?
Sometimes I make these in my spare time..

eT

 

I would not commit to a pc board yet. The circuit needs decoupling capacitors, attention to other unused pins, etc. Also, I would prototype it first to make sure the timing is correct for your application. You must use a scope to verify the output waveform.

ak

Thank you for the advice.
dj

 

Hi

Would you like a copy of the EL7104 to complete your simulation?
Sometimes I make these in my spare time..

eT

View attachment 172616

Hi eT
I am interested and please let me know where I can reach you to get more details.
dj

 

Hi eT
I am interested and please let me know where I can reach you to get more details.
dj

You can PM me or I can just post it here.

eT

 

That sounds like a 10 kHz square wave with a 1 us "up time". A 1 us pulse every 100 us. If yes, that is much easier than the schematic in post #1.

One - 1.000 MHz clock oscillator

Two - CD4017 Johnson counters in series, as in post #1.

Delete U10. Drive the U1 clock input with the 1 MHz signal directly.

U3 Carry output drives the U4 clock. U4 "D" input tied to Vcc. In this way, a 1 is latched into the flipflop every 100 cycles of the 1 MHz clock.

Connect O1 output of U1 to the U4 CLR input. The U4 Q output drives the external laser circuits.

Delete all of that other output gating goop.

The idea here is that the flipflop output is clocked to a 1 state every 100 us, and then is reset back to a 0 state 1 us later. The CLR input is hit 99 more times before the next output cycle starts, and the flipflop clock input remains high for another 49 us. Don't care. All that matters is the U4 CLR signal immediately before and after the positive-going clock input edge.

Where are you located?

ak

ak - If I want 0.1% duty cycle, do I only have to replace the 1MHz clock with 10MHz clock?
Thank you.
dj

 

Do you understand the meaning of frequency and duty cycle? If the frequency is 10 KHz and duty cycle is 1%, that means the signal is high for one microsecond outof every 100. So if the frequency is 10 KHz, the period is 100 usec and the on time is 1 usec.

Bob

 

ak - If I want 0.1% duty cycle, do I only have to replace the 1MHz clock with 10MHz clock?
Thank you.
dj

I was confused.
So for 0.1% duty cycle, add another CD4017B between the second CD4017B and CD4013B. Is this correct?

dj

 

ak - If I want 0.1% duty cycle, do I only have to replace the 1MHz clock with 10MHz clock?
Thank you.
dj

Hi

The CD4000 family max’s out at 5Mhz and that’s not guarantee’d. Probably much less.

eT

 

I am still not sure how to change the logic to apply 0.1% duty cycle for the 10kHz pulse frequency.

 

To get .1% duty cycle at 10KHz, the on time is 0.1 usec or 100 nsec. You would need a 10 MHz oscillator and an additional divide by 10 stage. Not to mention logic that can handle 10 MHz for the first divider.

Also, at that switching speed, the switch becomes more difficult.

Bob

 

I was confused.
So for 0.1% duty cycle, add another CD4017B between the second CD4017B and CD4013B. Is this correct?

Or between the first and second 4017's, yes - *conceptually*. For 0.1% DC, you need a divide-by-one-thousand function somewhere, somehow. The 4017 makes things easy because of its internal structure (technically it is a shift register with decoders, not a counter in the traditional sense). BUT, as noted, you are falling off the edge of the capabilities of standard CMOS parts. However, HC series parts will run above 20 MHz.

Power has not been discussed. Unlike standard 4000 series CMOS, the HC parts run on a max. of 5 V.

ak

 

If you ask me how I would solve this problem then I would use discrete digital electronics (no microcontroller).
And you may have guessed it, the 7400 series logic can play a useful role here.
Take a look at the 74LS123 datasheet for example.
You can drive the input with a 555 timer (or any other astable multivibrator).

 

Some confusion -

What I need is a circuit generating 10uSec, 100uSec pulse widths, +- 10% accuracy.

But then you ask for 1% duty cycle accuracy, then still later .1%.

If accuracy of pulse width only 10% its inconsistent to ask for .1 or 1% DC accuracy.

Can you clarify your specs ? And you are asking for pulse widths, do you care about frequency ?
Do you want to vary these outputs, frequency, duty cycle, pulse width ? If so method,
like potentiometer ? Do you need a readout to observe settings as you change them...?


Regards, Dana.

 

Can you clarify your specs ?

1.

the circuit ... is supposed to generate 10kHz pulse frequency with 1% duty cycle.

2.

how to change the logic to apply 0.1% duty cycle for the 10kHz pulse frequency.

ak