Hello , I am trying to simulate time domain reflectometry and recognise threw the pulse responce if the load is capacitative or inductive.
As you can see its not working .
Where did I go wrong with the concept.
what is the proper way to see threw the time responce if the load is capacitative or inductive?
Thanks.

 

What did you expect the result would be?

 

I expected negative peak with capacitor and positive peak with inductor.

 

Since when did a resistor represent a transmission line???

I think this is what you were trying to do... the red line is the output which you can see reflected back to the source approx 1.2uS later

 

Hello Irving , Yes exactly.
Do you have any manual regarding why inductive load causes negative peak?
whats happening in the reflection coeffient that causes it mathematickally.
Thanks.

 

Hello Irving , Yes exactly.
Do you have any manual regarding why inductive load causes negative peak?
whats happening in the reflection coeffient that causes it mathematickally.
Thanks.

Ummm, the sign of the imaginary part?

It's all to do with phase... and the standing wave in the TL.... I'm not that good with the math...

 

Could you give a basic example to this phrase its very intresting.How the phase plays a role?
"It's all to do with phase."

 

You are not applying a pulse to a delay line so why would you expect to see a reflection? This is not time domain reflectometry. All you are doing is applying a pulse through a resistor to a capacitor, so it charges up. You are applying a pulse to an inductor, so you see the back EMF,which then dissipates through the resistance of the inductor.
That is why I asked what you expected to see.

 

Could you give a basic example to this phrase its very intresting.How the phase plays a role?
"It's all to do with phase."

 

Hello ,Iwatched the video nsaspook posted.
I want to understand why the inductor gives positive peak while the capacitor gives negative peak.
What is the intuition in this?
Thanks.

Ummm, the sign of the imaginary part?

It's all to do with phase... and the standing wave in the TL.... I'm not that good with the math...

 

want to understand why the inductor gives positive peak while the capacitor gives negative peak.
What is the intuition in this?

Consider that to a rising current a capacitor looks like a short and and an inductor a high impedance... Therefore capacitor returns an in-phase pulse and an inductor an anti-phase response the amplitude of which is frequency and reactance related...

 

Hello Irving, is there an equivalent model for a "VIA" load so I could see the theory of how it responced to the excitation?
Thanks.

 

Would it not be better for you to understand more about TDR theory, rather than asking more and more questions? Here is an excellent article on the application and theory of TDR:

Understanding-Applying-TDR-Primer_48W-74128-0.pdf (tek.com)

 

Hello KeithWalker, this aritce is very good but the loads are lumped elements.
In real life we have a multilayer PCB.the digital signal passes threw traces and VIA from source to destination.
On one board being manufactured the square signal got distorted and its not good as the others.
I need to ivestigate it using TDR TDT.
The TDR TDT shows abnorality
Could you give me an example of such investigation?
So I could see the signal path where is the trace where is the VIAS?
Is there an article like the one in the link which explain the tdr of a signal passing threw traces and vias?
Thanks.
https://map-assets.tek.com/map-assets/asean/PDF/Understanding-Applying-TDR-Primer_48W-74128-0.pdf

 

Yef, every via is a discontinuity, a frequency-dependent impedance mismatch. If the vias are degrading the signal that badly then you need to remove them, or you need multiple vias at each location, to create a better impedance match. This is no trivial issue, and TDR isn't going to solve it for you, because it is frequency dependant. Each section of track is a transmission line with a characteristic impedance determined by it's relationship to other tracks and ground/power planes. Each is different, each needs to be matched to the one before and the one after; fixing this after the event will be nigh impossible. High-speed signals like this should have been routed first to avoid discontinuities and may need to be impedance controlled with guard traces each side. What sort of signal are we discussing? Can you show source and destination traces?

 

Yef, every via is a discontinuity, a frequency-dependent impedance mismatch. If the vias are degrading the signal that badly then you need to remove them, or you need multiple vias at each location, to create a better impedance match. This is no trivial issue, and TDR isn't going to solve it for you, because it is frequency dependant. Each section of track is a transmission line with a characteristic impedance determined by it's relationship to other tracks and ground/power planes. Each is different, each needs to be matched to the one before and the one after; fixing this after the event will be nigh impossible. High-speed signals like this should have been routed first to avoid discontinuities and may need to be impedance controlled with guard traces each side. What sort of signal are we discussing? Can you show source and destination traces?

Hello Irving ,its only a situation I saw on the side.
I was explained that this person has bad reflection coefficient plot and he was looking for the VIA PADs to see where is the faulty VIA.
He actually was watching on a microscope the pads of the VIA which are located on the outer layer of the PCB.
I need to practise to do the same .
could you please give an example for such faulty PCB structure which gives bad TDR so I'll get expirience with VIA TDR ?
Thanks.

 

could you please give an example for such faulty PCB structure which gives bad TDR so I'll get expirience with VIA TDR ?

Sorry, I've no idea how I can do that. It might be possible to create a simulation in LTSpice or some other simulator but how realistic that would be I have no idea...