Yes, that answers that. It probably even verifies point 14. In that case, no current limiting resistor is needed because the GPIO pin configured as input has high resistance and will limit the current flow out of the GPIO configured as output.



You are right though that I deviated from the original topic. It seemed like a natural transition but perhaps I need to repost the rest of the questions in another thread.

Have I correctly used the terms sink and source in the rest of the points above?

Is diode protection standard for GPIO pins?


Thanks,

Chris.

 

hi cm
All the PIC's and MCU's I know of have internal clamping diodes to +Vdd and 0V on their Input pins, they have a current limit of approx 10mA.
If you used the terms Sink and Source to identify a current path, most engineers would understand.

I only pointed out the topic deviation because if any one else making a Search regarding Outputs, would not be linked to your Thread.
Others will learn from reading your questions.

E

 

Hopefully, I'll add stuff without confusing the OP.

Just like with an OP-amp, CMOS inputs need a place for Ib (input current to the GPIO) to go. It can go to ground or Vcc. If it goes to Vcc, it consumes power.

You sometimes have to consider if Vcc is 0 or unpowered. There is an intrinsic diode which is why you see specs like -0.3 to Vcc+.3 for an input range. You also see a max current e.g. 5 mA. If Vcc is 0V or an input is > Vcc then current limiting resistors are required.

Going back to another logic family like TTL it was customary sometimes to not use a simple pull-up, but rather a voltage divider, because you could make the inputs switch faster. You had thresholds like < 1.6 for a logic low and > 2.5 or so for a high. If you biased the input of the gate to 3V, it could switch faster. With buses you could have passive (just resistors) and active termination.

 

Is diode protection standard for GPIO pins?

Yes, not only for GPIO pins of microcontrollers, but for nearly all pins of all CMOS integrated circuits as well as most bipolar integrated circuits. They are there to reduce susceptibility to damage caused by electrostatic discharge (ESD).

 

In most of the cases I have seen thus far ( I am trying to understand transistors now) , the concept of pull up and pull down seems to apply as well.

For example, in the case of a common emitter circuit NPN transistor, there is a resistor on the collector which seems to "pull up" the collector voltage to Vcc. When the base voltage is HIGH, CE resistance is LOW (closed switch) and so C is connected to GND (LOW). When the base voltage is LOW, CE resistance is HIGH (open switch) and so the pull up resistor pulls C to Vcc (HIGH). It seems CE is behaving as a voltage controlled resistor. The higher the base voltage, the lower the CE resistance. The lower the CE resistance, the less of a voltage drop happens across it and the more the voltage drop happens across the collector resistor it is in series with, so the collector voltage approaces GND. This also explains the inverse phase relationship.

In the common collector circuit NPN transistor, there is a "pull down" resistor on the emitter pulling it down to GND. If the base voltage is HIGH, CE resistance is LOW (closed switch) and so C is connected to Vcc (HIGH). When the base voltage is LOW, CE resistance is HIGH (open switch) and so pull down resistor pulls the emitter down to GND (LOW). This explains the in phase relationship.

It seems that it could be generalized that the pull up and pull down way of reasoning out the mechanics of a circuit is a very good abstraction of the Ohm's Law analysis. Its faster to think in those terms ( if the switch is open, the output is pulled high/low) rather than Ohm's Law and voltage division (resistor is in series with high/low impedance, therefore voltage division.....) .

This is again a bit of a deviation from the topic but is the CE of a transistor really behaving like a voltage controlled resistor, in which case the voltage drop across it would vary depending on the base voltage? I am confusing this with other articles that state there is a fixed .1 voltage drop across the CE but that might only apply if the transistor is saturated, not when in active mode.

Thanks,
Chris

 

hi Chris,
Typically at transistor is operated in the Active mode or the Saturation mode.
The Active mode is where a transistor is biassed in such as way the Collector voltage is half the supply voltage Vdd/2 . [Class 'A']
Any change in Base current/voltage will cause a greater change in Collector current and the Vce voltage, that is an amplifier.

In the Saturation mode the transistor is being used as a switch, either Off or hard On, saturated.
The Base current/voltage either 0V or say 0.7V or higher in order to drive the transistor into saturation.

E

 

hi,
Ref Output pin pullup or pull down.

Typically a PU resistor is required on a devices Output pin, that does not have an internal connection to +Vdd.
The device is specified as having a Open Collector or Open Drain, say a NPN transistor or NMOS FET.

Likewise a PD is used on a devices Output pin that does not have an internal connection to 0v.
The device is specified as having a Open Collector or Open Drain, say a PNP transistor or PMOS FET.

Many IC devices have internal active pull up and pull down Outputs, a totem pole arrangement of a NPN, PNP or NMOS, PMOS FET.

E

 

Yes, the transistor is behaving as a variable resistor.

Instead of calling the resistors pull-up and pull-down resistors, sometimes it is appropriate to called them load resistors. Now we can consider the behavior of the transistor with respect to the load line diagram.

The point where the load line hits the VCE axis is the maximum voltage supplied by the power supply. Hence at Ic = 0, VCE = VCC.
The point where the load line hits the IC axis is the maximum current that the circuit can supply assuming that VCE = 0 and the resistance across the transistor is zero. This max current is VCC/RL at VCE = 0 where RL = RC + RE.

The load line defines the locus of all operation conditions of the transistor in this circuit. Thus, IC and VCE must fall on the load line. Where the transistor falls on the load line will depend on the bias voltage on the base and hence the base-emitter current, IB.

The static resistance of the transistor, from collector to emitter, can be calculated as VCE/IC at the specific bias condition.

 

This is again a bit of a deviation from the topic but is the CE of a transistor really behaving like a voltage controlled resistor, in which case the voltage drop across it would vary depending on the base voltage?

Yes, you can think of it as acting like a voltage-controlled resistor, but that analogy is both simplistic and flawed: it would be much more accurate to think of the transistor as acting like a voltage-controlled current source (or sink) because when operating in the active region (i.e., neither cutoff nor saturated), collector current depends mainly on base-emitter voltage and only slightly on collector-emitter voltage.

And for most purposes, it's more accurate still to consider the transistor as acting like a current-controlled current source in which the collector current is determined primarily by the base current, through the factor β or Hfe (current gain).

I am confusing this with other articles that state there is a fixed .1 voltage drop across the CE but that might only apply if the transistor is saturated, not when in active mode.

There is no fixed CE voltage drop in saturation; that notion may sometimes suffice in practice for roughly estimating voltages and currents in a circuit, but it is definitely NOT appropriate if you're trying to understand how transistors operate.

Vce(sat) depends on both base current and collector current. If you look at a transistor data sheet such as this one for a 2N3904, you'll see that relationship in Figs. 16 and 17 on page 6.

 

"Typically a PU resistor is required on a devices Output pin, that does not have an internal connection to +Vdd."

MCU pins that are configured as output must have an internal connection to either +Vdd or GND. That's how they can provide a HIGH (source ) or LOW (sink) signal. In that particular case, then there is no need for a PU or PD resistor?

Thanks,
Chris

 

MCU pins that are configured as output must have an internal connection to either +Vdd or GND.

Why have you misquoted my post by omitting the word pin in order to make a point.?

MCU pins that are configured as output must have an internal connection to either +Vdd or GND. That's how they can provide a HIGH (source ) or LOW (sink) signal. In that particular case, then there is no need for a PU or PD resistor?

My post #27 was:
Typically a PU resistor is required on a devices Output pin, that does not have an internal connection to +Vdd.

 

"Typically a PU resistor is required on a devices Output pin, that does not have an internal connection to +Vdd."

MCU pins that are configured as output must have an internal connection to either +Vdd or GND. That's how they can provide a HIGH (source ) or LOW (sink) signal. In that particular case, then there is no need for a PU or PD resistor?

Thanks,
Chris

The internal pull-up supplied by the MCU is considered a "weak" pull-up in the range of about 33kΩ. This eliminates the need for external pull-up resistors. Depending on specific circuit requirements this might not be sufficient for the circuit to function reliably. In such cases, external pull-up resistors would be required.

 

Sorry, did not mean to offend or misquote. The question is really : Do I need a pull up or pull down on a MCU output pin? I know it is necessary for an MCU input pin. I thought (guessed )an MCU output pin provides a HIGH or LOW by simply connecting the Vcc or GND to the pin. If the answer to the question is yes, then I have misunderstood a concept or two along the way. Bear in mind that the question is specifically for MCU output pins like for example the Pi or Arduino.

Thanks,
Chris

 

Thought I would add a few points here.

First. always consult the datasheet. They will tell you how the I/O pins work in great detail. The datasheet is your friend...

A pullup on an MCU pin is basically for when it is programmed to be an input. Typically, the PUs are weak as MrChips mentioned though the range of effective resistance is pretty wide - some are as high as 100K and I recall seeing, in a number of datasheets, something to the effect that a specific PU resistance isn't guaranteed. Older PICs, for example often had 50K nominal.

On output, most pins have a push-pull arrangement (high side and low side drivers, no PU/PD needed). But one should always look at the datasheet. Typically they show an equivalent schematic for the output (and input) pins. It's not uncommon for a given MCU to have several different pin driving schemes. Also, check the data sheet for the amount of current supported. It's not always the same for every pin. The AVR micros used for the Arduinos all have push/pull on output, no PU/PD needed. But consult the datasheet.

By the way, did I mention to look at the datasheet?

 

Sorry, did not mean to offend or misquote. The question is really : Do I need a pull up or pull down on a MCU output pin? I know it is necessary for an MCU input pin. I thought (guessed )an MCU output pin provides a HIGH or LOW by simply connecting the Vcc or GND to the pin. If the answer to the question is yes, then I have misunderstood a concept or two along the way. Bear in mind that the question is specifically for MCU output pins like for example the Pi or Arduino.

Thanks,
Chris

You still have some misconceptions.

To state that "it is necessary for an MCU input pin" is not correct.

You need to learn about the different types of logic outputs, as follows:

1. Totem pole. This applies to both bipolar transistor technology (BJT) and CMOS FET technology. This is also known as push-pull output.
2. Open collector output. This applies to BJT.
3. Open drain output. This applies to FET and CMOS technology.
4. Tri-State output.

MCU INPUTS
If the source of the signal is a totem pole output gate then the MCU input pin does not require pull-ups. A totem pole output can both source and sink current. That is why is also known as push-pull output.

If the source of the signal is an open collector or open drain output, then yes, you need an external load. Open collector and open drain can only sink current (pull). It cannot source current (push).

MCU OUTPUTS
If the MCU output pin is totem pole then you do not need an external load resistor. Most MCU output pins are totem pole outputs.
If the MCU output pin is open collector or open drain then you need an external pull-up load resistor. MCU output pins are rarely open collector and open drain.

The most common places where you encounter open collector and open drain outputs are analog comparator ICs and opto-isolators.

TRI-STATE OUTPUT
Some MCU output pins and logic gates such as bus drivers have tri-state outputs. This means that it is possible to disable the output pin entirely and it is as if the output pin is disconnected and not in the circuit at all. In such cases, a logic LOW or logic HIGH is supplied by external resistors or by another gate whose output pin has been enabled.

 

hi Chris,
You did not offend me, sorry if I misunderstood your meaning.
Eric

 

The question is really : Do I need a pull up or pull down on a MCU output pin?

Maybe, maybe not; it depends on what type of output it is. Most commonly, MCU outputs are of the "push-pull" (a.k.a. "totem-pole") type, in which there is an NMOS transistor that can pull the pin down to GND, plus a PMOS transistor which can pull the pin up to Vdd. One or the other is always on, thus forcibly making the output high or low. Obviously, no pullup or pulldown resistor is needed.

Some MCU outputs, however, may be of the "open drain" type, in which the PMOS transistor is omitted; in this case, the MCU can only pull its output low and something external to the MCU is needed to pull the output high when the MCU outputs a "1" to that bit. Most of the time, that something is a pullup resistor.

I know it is necessary for an MCU input pin.

Wrong, wrong, WRONG! A pullup resistor is required on an MCU input ONLY if whatever is driving the pin (for example, a pushbutton switch to GND) is capable of only forcing one of the two valid logic states. If whatever is driving the MCU pin is capable of driving the pin both high and low, no pullup resistor is needed.

EDIT: Dang, MrChips beat me to it.

 

Thanks guys, this clears things up a bit. Didn't really know what a totem pole configuration was until today.

I have found one thread discussing the RPI's GPIO configured as outputs as not requiring pull up or pull down. That means the outputs are push pull (totem pole).

I also know that a RPI GPIO output pin can be connected directly to a GPIO input pin without need for a pull up or pull down resistor or even a current limiting resistor. This confirms that the output pin is totem pole.

If whatever device is connected to the input pin of a RPI can output both a LOW or HIGH ( as is the case when the device is a push pull GPIO pin configured as output) then no need for a pull up/down resistor. If the device connected to the GPIO input pin acts merely as a switch to either GND or Vcc but not both, then you need a pull up or down resistor to pull the input to the opposite state when the device is in "open switch" mode.

The above seems to mesh with everyone's conclusions so far as I can think.

Thanks,
Chris

 

The above seems to mesh with everyone's conclusions so far as I can think.

That's it, EXACTLY. You've got it.