I just finished the chapter regarding current and voltage division using parallel and series resistors and am trying to extend the logic towards pull up and pull down resistors. I uploaded a couple of schematics that describe a pull up resistor circuit. I think they are identical since in the first, all bottom legs of the circuit go to common ground which is the battery negative terminal. I hope that is correct. If that is correct, then I think the following analysis applies.
The resistor in parallel with the switch actually represents the internal resistance of a microcontroller which is labeled as R2. The box enclosing it represents the microcontroller. The pullup is labeled R1. The microcontroller will have a ground connection and so will one end of the switch. Since both are zero reference voltage, I represented the two "ground" connections as being connected, thus forming what looks like a parallel connection between the switch and the microcontroller.
If the switch is in the open position, the resistance in the parallel circuit amounts to the resistance of R2 only. R2 would be in series with R1 and so voltage division occurs with R2 getting the majority of the share of the voltage due to its higher resistance. R2 will therefore get close to 3.3 Volts ( measured from ground to GPIO pin ) while R1 will get close to 0 volts across it. This will be the HIGH state of the GPIO being set. If the switch is closed, then we can think of R2 being in parallel with bare wire ( bare wire in this scenario will be a "resistor" close to zero resistance ) and therefore, a almost negligible resistance in parallel with the microcontroller resistor would mean the parallel circuit's total resistance would be close to zero, shifting the voltage division in favor of R1, that is, R1 will now have close to 3.3 volts across it while R2 and hence the microcrontroller will have close to zero between the GPIO and common ground, thus setting the GPIO to the LOW state. I have to envision the circuit in its complete form so I can trace the flow of current. Is there a flaw in the analysis?
The resistor in parallel with the switch actually represents the internal resistance of a microcontroller which is labeled as R2. The box enclosing it represents the microcontroller. The pullup is labeled R1. The microcontroller will have a ground connection and so will one end of the switch. Since both are zero reference voltage, I represented the two "ground" connections as being connected, thus forming what looks like a parallel connection between the switch and the microcontroller.
If the switch is in the open position, the resistance in the parallel circuit amounts to the resistance of R2 only. R2 would be in series with R1 and so voltage division occurs with R2 getting the majority of the share of the voltage due to its higher resistance. R2 will therefore get close to 3.3 Volts ( measured from ground to GPIO pin ) while R1 will get close to 0 volts across it. This will be the HIGH state of the GPIO being set. If the switch is closed, then we can think of R2 being in parallel with bare wire ( bare wire in this scenario will be a "resistor" close to zero resistance ) and therefore, a almost negligible resistance in parallel with the microcontroller resistor would mean the parallel circuit's total resistance would be close to zero, shifting the voltage division in favor of R1, that is, R1 will now have close to 3.3 volts across it while R2 and hence the microcrontroller will have close to zero between the GPIO and common ground, thus setting the GPIO to the LOW state. I have to envision the circuit in its complete form so I can trace the flow of current. Is there a flaw in the analysis?
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