Pull up and pull down resistors as a specific case of voltage division

Thread Starter

cmisip

Joined Sep 23, 2017
89
I just finished the chapter regarding current and voltage division using parallel and series resistors and am trying to extend the logic towards pull up and pull down resistors. I uploaded a couple of schematics that describe a pull up resistor circuit. I think they are identical since in the first, all bottom legs of the circuit go to common ground which is the battery negative terminal. I hope that is correct. If that is correct, then I think the following analysis applies.

The resistor in parallel with the switch actually represents the internal resistance of a microcontroller which is labeled as R2. The box enclosing it represents the microcontroller. The pullup is labeled R1. The microcontroller will have a ground connection and so will one end of the switch. Since both are zero reference voltage, I represented the two "ground" connections as being connected, thus forming what looks like a parallel connection between the switch and the microcontroller.

If the switch is in the open position, the resistance in the parallel circuit amounts to the resistance of R2 only. R2 would be in series with R1 and so voltage division occurs with R2 getting the majority of the share of the voltage due to its higher resistance. R2 will therefore get close to 3.3 Volts ( measured from ground to GPIO pin ) while R1 will get close to 0 volts across it. This will be the HIGH state of the GPIO being set. If the switch is closed, then we can think of R2 being in parallel with bare wire ( bare wire in this scenario will be a "resistor" close to zero resistance ) and therefore, a almost negligible resistance in parallel with the microcontroller resistor would mean the parallel circuit's total resistance would be close to zero, shifting the voltage division in favor of R1, that is, R1 will now have close to 3.3 volts across it while R2 and hence the microcrontroller will have close to zero between the GPIO and common ground, thus setting the GPIO to the LOW state. I have to envision the circuit in its complete form so I can trace the flow of current. Is there a flaw in the analysis?
 

Attachments

ericgibbs

Joined Jan 29, 2010
8,887
hi cm.
The input resistance/impedance of a MCU CMOS Input is many mega Ohms, so as far as the much lower values of the pull up resistor the MCU input resistance can be considered infinite.
E
 

MrChips

Joined Oct 2, 2009
19,425
You are on the right track.
For a complete analysis, you need to examine the data sheet to the input pin of the device.
This will supply max VIL and min VIH at specified input currents.

If you are interfacing with a switch, these specifications are all that you need.

If you are interfacing from another logic gate, then you need to examine the source and sink current capability of the output pin.
 

Thread Starter

cmisip

Joined Sep 23, 2017
89
I am extending the logic to a pull down resistor scenario. I came up with a symmetrical schematic for both the situation when a pull up is used and when a pull down is used. The schematic if correct seems to unify the concepts and if so maybe I could put this part of the lesson behind me. R1 is the pull up or pull down resistor. R2 and R3 represent the internal impedance of the MCU ( I am just guessing that the MCU might generally have a configuration like this because it seems to make sense with the current designs of pull up and pull down schematics I found on the internet ).

Lets say R1 is 10K and R2 and R3 are 1000K so parallel resistance will be 1÷((1÷10000)+(1÷1000000)) = 9900. I am not really considering current (I) values right now but I do realize that the current that passes through the GPIO needs to be a specific amount based on the specs of the MCU pins. I am just concerned about the voltages right now as that is what defines a HIGH or LOW state.

PULL DOWN
The first schematic is pull down. Here parallel 1 is the circuit with the switch in parallel to R2. With the switch open, the resistance of Parallel 1 is simply R2 (1000K) which is in series with the Parallel 2 (9.9K). The voltage divider would favor Parallel 1 which will have a significant voltage drop while Parallel 2 would have a minimal voltage drop. This will make the voltage measured from GPIO to GND to be close to zero.
Due to the high value of R2 when the switch is open, there is not a large current flowing through the circuit.

With the switch closed, Parallel 1 would have zero resistance while Parallel 2 would have 9.9K which shifts the voltage division in favor of Parallel 2. There would have been minimal voltage drop across Parallel 1 which means the voltage measured from GPIO to GND will be close to 3.3 Volts.

PULL UP
The second schematic is pull up. With the switch open, Parallel 1 is 9.9 K while Parallel 2 s 1000K shifting the voltage division in favor of Parallel 2. There will not be a significant voltage drop across Parallel 1 so that voltage measured from the GPIO to GND will be close to 3.3 Volts.
Due to the high value of R3 when the switch is open, there is not a lot of current flowing through the circuit.

With the switch closed, Parallel 2 now becomes effectively zero resistance, while Parallel 1 is 9.9 K. This shifts the voltage division in favor of Parallel 1 which would mean the voltage measured across Parallel 2 (GPIO to GND ) would be close to zero.

Anything wrong with this analysis?

Thanks,
Chris
 

Attachments

ericgibbs

Joined Jan 29, 2010
8,887
hi cm,
You are making the problem over complicated when you are considering MCU inputs, which is a CMOS technology device.
Consider that the input impedance of CMOS is very, very high , many mega ohms and typically the PU and PD resistors are in the kilo ohm range, so the input impedance has very little effect on the input voltage.
E
 

Attachments

Last edited:

philba

Joined Aug 17, 2017
960
I was under the impression that pull up size was more related to noise immunity. The higher the value, the lower the noise immunity. Conversely the lower the value causes more current draw.
 

AnalogKid

Joined Aug 1, 2013
8,157
I was under the impression that pull up size was more related to noise immunity. The higher the value, the lower the noise immunity. Conversely the lower the value causes more current draw.
Correct. Radiated noise induces a current into a wire or circuit. that current develops a voltage across a resistance in the circuit. The circuit elements, like a microcontroller input, respond to voltage levels. So, one way to approach the "correct" value for a pull up resistor is to consider the amount of noise, and how large a resistance it would take for the induced voltage to exceed the uC input threshold voltage and cause a false input signal. Then make the pull up resistor smaller than that. However, the smaller the pullup resistor is the larger the *intentional* signal current needs to be to force a correct input signal. It is a trade off.

ak
 

Thread Starter

cmisip

Joined Sep 23, 2017
89
Thanks for the replies. I am realizing now too that in the schematics above, when R2 and R3 value increases upwards to multi megaohms, then its contribution to the parallel circuit with either the switch or R1 diminishes such that in the case where R2 is parallel to R1, the parallel resistance is 9.9K which is approximately 10k or R1's resistance. As R2 and R3 increase, the value of the parallel resistance approaches the value of R1. It seems for all intents and purposes, the MCU internal resistance could be ignored and this could be treated simply as voltage division between the switch and R1 (pull up or pull down) . In the case of the PULL DOWN and SWITCH OPEN, the majority of the voltage drop would be between the terminals of the switch, putting the GPIO pin at close 0 volts. In the case of the PULL DOWN and SWITCH CLOSED, the majority of the drop occurs across R1 putting the GPIO pin at close 3.3 Volts. In the case of the PULL UP and SWITCH OPEN, the majority of the voltage drop occurs at the switch terminals, putting the GPIO pin at close to 3.3 Volts. In the case of the PULL UP and SWITCH CLOSED, the majority of the drop occurs at R1 putting the GPIO pin at close to 0 Volts.

I could not have arrived at this conclusion without imagining the "apparent" connections of the "resistors" in the MCU, because it looked like an open circuit when the SWITCH OPEN. Another possible solution besides the imagining of the MCU internal resistors, that allows for the circuit to be closed and hence allow current flow would be to pretend that the OPEN SWITCH has current leakage, that is, in its open state it is not infinite resistance but a small amount of current crosses the switch. These two possibilities would seem to be the reason for the floating voltage at the GPIO pin. Also from the analysis above, since the internal MCU resistance is not really known but it is a high value and since the parallel circuit's resistance ( the parallel circuit with the switch ) really can be approximated as the value of the pull up and pull down resistor, no specific computations are necessary for pull up and pull down values. That's why it is simply a broad range.

The switch of course would be some type of sensor that outputs close to zero volts or close to 3.3 volts that can be sensed by the GPIO pin as either a HIGH or LOW state.

My next question would be then do all sensors have some kind of background current leakage that closes the circuit or is closing of the circuit accomplished by the "internal resistors" of the MCU? Is this what you call noise?

Thanks,
Chris
 

ericgibbs

Joined Jan 29, 2010
8,887
hi,
An open circuit Input pin of a CMOS input is often said to be 'floating'.
Placing ones hand or any other object close to a floating pin can set the pin to assume an indeterminate state ie: the MCU could see a logic hi or logic low.
This is due to pick of the electric field surrounding the hand or object onto the floating HiZ input pin.

The purpose of a PU is ensure that the MCU see's a Hi when the switch from Input to 0v is Open, it is not floating.
A PD ensures that the MCU Input see's a Low when the switch between the Input and +v is Open.

A driving sensor would only normally have a PU if the sensor Output is an Open Collector.[ ie: the sensor does not have its own internal PU]

E
Edit
Added: line 4
 
Last edited:

Thread Starter

cmisip

Joined Sep 23, 2017
89
So the float value is sensitive to electric fields but the fact that there is a floating value probably implies the circuit is closed even with the switch open ( I mean, a very small amount of current flows to the GPIO from the switch side or from the MCU side) ?

It seems also that at the junction of the GPIO pin with the switch and the PU or PD resistor, there is current division happening in the case of a GPIO pin configured as input. With the switch closed, enough of the current needs to flow into the GPIO pin ( within a threshold ) but some of it will flow out of the PU or PD resistor. Is this what it means to "defeat" the PU or PD? That is to say, there should be enough current left to sink to the GPIO pin. In this case a low value for a PU or PD resistor would cause too much current to flow away from the junction. I guess the question really is, is there a current threshold that needs to be satisfied to set a GPIO input pin to HIGH or LOW, is it is simply set by voltages? This then also implies that the current (I) calculation is simply for the benefit of keeping the current at the GPIO within a safe threshold but does not have any effect on the GPIO state since that is voltage dependent. If the current is not important except to be kept within a safe threshold, then does "defeating" the PU or PD mean the voltage division ( when the switch is closed ) between the switch and the PU/PD should allow for the expected change of STATE ( meet the threshold for either LOW or HIGH state )?

I suppose this also implies that a GPIO pin configured as output does not need any PU or PD as there is active circuitry pushing voltage out.
Thanks,
Chris
 

ericgibbs

Joined Jan 29, 2010
8,887
It is possible to have an electric field/voltage difference without any current flowing but you cannot have current flow without a voltage potential.

Such small currents flow in CMOS logic inputs that it is reasonable to assume CMOS logic is voltage controlled.

A MCU GPIO output is either High or Low as set by the internal state of the MCU, it can source or sink current, typically a maximum of 20mA.
 

Thread Starter

cmisip

Joined Sep 23, 2017
89
If we can completely ignore the resistances in the MCU with this analysis, then the pull up or pull down resistor is actually in series with the switch and therefore acts as current limiter. The current that goes in the GPIO pin cannot be higher than the current that is traversing the pull up or pull down. So with a pull up or pull down resistor, you dont really need another current limiting resistor before the GPIO pin. Is this correct?

Thanks,
Chris
 

ericgibbs

Joined Jan 29, 2010
8,887
hi,
The resistor in series with switch does limit the current, but it is also there to ensure that the Input assumes a Hi or Low when the series switch is Open.
Do not consider the current in/out of a CMOS logic input, it as I have said, close to zero for all practical purposes.

It is permissible to connect an unused CMOS directly to the +Vdd or 0V without any limiting resistor.
In fact any unused Inputs are generally tied Low, not left 'floating'

Some MCU Inputs have internal PU of approx 50k, which can be enabled/disabled by the program.
 
Last edited:

OBW0549

Joined Mar 2, 2015
3,028
If we can completely ignore the resistances in the MCU with this analysis, then the pull up or pull down resistor is actually in series with the switch and therefore acts as current limiter.
The function of a pullup/pulldown resistor has absolutely nothing whatsoever to do with current limiting; the pullup resistor is there only to establish a default logic state in the absence of something (such as a switch closure) acting to impose the opposite logic state. That is ALL it is there for, nothing more.

CMOS inputs (and this includes microcontroller GPIO pins configured as inputs) are effectively open circuits for any input voltage between Vss and Vdd. They do not draw ANY current at all other than leakage current which is often just a few nanoamps, ranging up to a few microamps at most, provided the input voltage is within those limits.

The ONLY circumstance in which a series current limiting resistor is necessary for CMOS inputs is when the device driving the input is capable of driving it to a voltage more positive than Vdd or more negative than Vss; in that case, without a current limiting resistor the internal protection diodes on the CMOS input can begin to conduct and can draw excessive current that may cause erratic device operation or even damage the device.

The current that goes in the GPIO pin cannot be higher than the current that is traversing the pull up or pull down.
Technically true, but irrelevant: the current going into the GPIO pin also cannot be higher than what the GPIO pin itself draws, which for nearly all practical purposes is ZERO.

So with a pull up or pull down resistor, you dont really need another current limiting resistor before the GPIO pin. Is this correct?
No: you don't need a current limiting resistor, PERIOD, except as noted above.
 

Thread Starter

cmisip

Joined Sep 23, 2017
89
I am trying to understand the mechanics involved from within the framework of Ohm's Law and Kirchoff's law, not simply to know what's supposed to happen. To that end, I am trying to envision the complete circuit so the path of the current can be traced. I am also trying to find a synthesis of the information available on the internet regarding this topic. Let me summarize what I think I understand so far. I might be stretching things too far. Please correct me If I am wrong.

1. GPIO pins configured as input have a high impedance connection internally to Vcc and to GND. It's high impedance limits current through it. No need for a current limiting resistor. The GPIO pin is voltage sensing so the amount of current through it is not relevant.

2. A GPIO pin that is pulled high by a pullup resistor has minimal current going through it ( PATH: Vcc -> pullup resistor -> GPIO pin -> MCU's internal resistance -> GND ). There is minimal voltage drop across the pull up resistor but maximal voltage drop at the high impedance GPIO -> MCU -> GND. Therefore the GPIO reads HIGH.

3. A GPIO pin that is pulled down by a pull down resistor has minimal current going through it ( PATH: Vcc -> MCU's internal resistance -> GPIO -> pull down resistor -> GND ). There is maximal voltage drop across the high impedance Vcc -> MCU -> GPIO, but minimal voltage drop across the pull down resistor. Therefore the GPIO reads LOW.

4. In the pullup scenario, closing the switch provides an alternate path to the current which now flows from Vcc -> pullup resistor -> (GPIO) ->switch -> GND. There is maximal voltage drop across the pull up resistor resulting in GPIO voltage reading LOW. The high internal impedance of the GPIO configured as input limits current flow through it. The pullup resistor seems to set a maximum current value, but very small amount will actually pass through the GPIO to the MCU because the lower resistance switch pulls the current away. In the absence of the pullup resistor it is safe to connect to connect a 3.3v or 0v potential to the GPIO because of its high internal impendance. But the pull up is necessary so the GPIO remains at HIGH.

5. In the pulldown scenario, closing the switch provides an alternate path to the current which now flows from Vcc -> switch -> (GPIO) -> pulldown resistor -> GND. There is minimal voltage drop across the switch and maximal voltage drop across the pull down resistor resulting in GPIO voltage reading HIGH. The pulldown resistor seems to set a maximum current value, but very small amount will actually pass through the GPIO to the MCU because the lower resistance pulldown resistor pulls the current away. In the absence of the pulldown resistor it is safe to connect to connect a 3.3v or 0v potential to the GPIO because of its high internal impendance. But the pull down is necessary so the GPIO remains at LOW.

6. A GPIO configured as output must have low impedance because if it did not, then there would be a very low current going through the GPIO. If that is the case, it wont be able to power low amperage devices like LED's. With a GPIO pin configured as output, a current limiting resistor is required to keep the current through the GPIO pin within safe levels.

7. A GPIO pin can source and sink currents. This has to do with the direction of the current through the pin.

8. A GPIO input pin pulled high, if presented with 0 volts must "source", meaning it will pull current from its connection to Vcc and out the GPIO pin to GND.

9. A GPIO input pin pulled low, if presented with 3.3 volts must "sink", meaning it will drive the current down through its internal connection to GND.

10. A GPIO output pin could also source and sink depending on wether we want it to output a HIGH or LOW.

11. Potential difference drives the flow of current and direction. If a GPIO input pin pulled high is presented with a HIGH voltage, then there is no current flow. If a GPIO input pin pulled LOW is presented with a LOW voltage, then there is no current flow.

12. If we ask a GPIO pin to output a HIGH, then it becomes the source of positive current. The circuit will be completed by a connection to GND after the LOAD. In this same configuration, if we ask the GPIO pin to output a LOW, then virtually no current flows since the LOAD is connected to GND.

13. If we ask a GPIO pin to output a LOW, then it becomes the destination of positive current. The circuit will be completed by a connection to Vcc before the LOAD. In this same configuration, if we ask the GPIO pin to output a HIGH, then virtually no current flows since the LOAD is connected to Vcc.

14. A GPIO pin configured as output can be connected to a GPIO pin configured as input and there will be no need for a current limiting resistor in between because the GPIO pin configured as input, by virtue of its high impedance will be limiting the current flowing out of the GPIO pin configured as output.

15. Number 14 is one way that multiple MCU's might communicate as long as their Vcc's are the same ( both 5 V or 3.3 V) and their GND's are connected. But even if the Vcc's are not the same , a current limiting resistor could serve as a voltage divider if connected between the two GPIO pins. This is probably also how logic gates are connected.

16. A current limiting resistor in front of a GPIO input pin could serve to limit current through the pin and protect it in the case that a larger voltage than what it is rated for is applied to it ( for example 5V is applied to 3.3 V device ).

17. Another instance a current limiting resistor in front of a GPIO input pin is a good idea is if the GPIO is configureable as both input and output and the operating system might have a default state for the pin as OUTPUT. In which case, the current through the GPIO may exceed the safe threshold.


Thanks,
Chris
 
Last edited:

Thread Starter

cmisip

Joined Sep 23, 2017
89
18. There is probably an option to activate internal pull ups and pull downs for some boards and using external or internal would be equivalent. However probably not a good idea to use both at the same time as the resistors would be in parallel and thus will reduce their effective resistance leading to higher current through the GPIO.

Thanks,
Chris
 

ericgibbs

Joined Jan 29, 2010
8,887
hi cm,
I got as far as Question 8, in writing an answer, but then I gave up!.
You keep referring to the GPIO's Input pin current, you are over thinking the problem.

Lets us recap:
Forget and do not include the MCU GPIO CMOS Input/Output current in your questions/calculations.
It is so small as to have almost zero effect on the calculations and can be ignored.

Redo your reply, it should be limited to about three short paragraphs.
Add in the summary, that the GPIO Input current has been assumed to be zero.

E
 

Thread Starter

cmisip

Joined Sep 23, 2017
89
Basically you can ignore 1-5. That's just me summarizing what I thought was happening in the circuit in the schematic I posted.

I have seen number 6 in action.

From 7 -18 , I am not sure if the conclusions are correct. I am assuming that a GPIO pin that is configured as output has low impedance to its internal connection to Vcc OR its internal connection to GND. I am not sure if I was correct in my understanding of sourcing and sinking. I dont know how I would simplify points 7-18 further. A comment on wether those points are correct or not would suffice.

An elaboration on point 17. If there was no current limiting resistor in that scenario, then switching a GPIO (via software control) from being an input to output by mistake in the case that it outputs a HIGH and it is connected to device that is outputting a LOW, then there is a short circuit.

Thanks,
Chris
 

ericgibbs

Joined Jan 29, 2010
8,887
[QUOTE6. A GPIO configured as output must have low impedance because if it did not, then there would be a very low current going through the GPIO. If that is the case, it wont be able to power low amperage devices like LED's. With a GPIO pin configured as output, a current limiting resistor is required to keep the current through the GPIO pin within safe levels.QUOTE]

hi,
For Q6.
The maximum Output [Source] and [Sink] currents are specified in a PIC's datasheet as ~25mA.

If you try to draw more than 25mA, you could damage the PIC's output driver.
Knowing the required current for the load, the Output pin is driving, the value of the series current limiting resistor is calculated.

When I calculate Output resistor values I do not think in terms of 'PIC impedances', I use the datasheet as a guide, which states the maximum allowed Source/Sink current.
The same apples when using the Output pin as a 'current 'Sink'.

Does that answer your Q6 query.?

Ref this image,

E
BTW: I would remind you, that your Thread Title was querying PU/PD, not Output pins.
 

Attachments

Last edited:
Top