Phased and Sequential Clock Generation

Thread Starter

danadak

Joined Mar 10, 2018
4,057
If you have to grind out simple clock schemes for a design a single chip, using a fraction of its resources,
can produce a number of clock variants. Note chip has a lot of other stuff, like ARM core, Analog (SAR, DelSig,
Vref, DAC, Mixer, OpAmps, Comparators, Muxes....), digital from simple gates, LUT , flops, to PWM, Timers, DSP.
Drag and Drop design, right click to config.

Clock designs like this require no code. I think, for example, one could do a 64 bit seq clk on onechip as
example. Basically an N clk type capability.

Also by using LUT one can make very unusual phased/sequenced arrangements. So for example you could
generate within a clock phase a sequence of clocks.....


1586738900984.png


Regards, Dana.
 

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Thread Starter

danadak

Joined Mar 10, 2018
4,057
The states in the system are 4 for high period, 4 for low, total 8 states, due to phases.

1586729753004.png


Regards, Dana.
 

joeyd999

Joined Jun 6, 2011
4,431
ϕ3 and ϕ4 are complements of ϕ1 and ϕ2, respectively. Therefore, they are not required as feedback into the LUT (i.e. they are redundant).

ϕ1 and ϕ2 are sufficient to describe any given state.

Therefore, 4 states, 2 registers, and 4 outputs.
 

Thread Starter

danadak

Joined Mar 10, 2018
4,057
Bear with me, as you can see I am not a logic expert.

The lower 3 bits of the LUT generate the states, the upper 4 bits do the decode.

Can you show me an equivalent LUT table for 2 bits generating the phases ? Just
a text table would do.

Is it a 2 bit LUT with inverters to gen the duplicate phases ?


Regards, Dana.
 

Thread Starter

danadak

Joined Mar 10, 2018
4,057
i see whats wrong. The timing diagram I showed does not reflect the overlapping phase shift
each clock exhibits. I corrected that post.

Each clock is phase shifted by 45 degrees, 50%duty cycle, so there is no simple inverted relationship between any two phases.

This is the output for the LUT encoding I used. Main criteria was 4 clocks, 50% duty cycle, phase shifted.

The clock phases are simple decode, not used as LUT fdfbk.

1586737843387.png

Regards, Dana.
 
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joeyd999

Joined Jun 6, 2011
4,431
i see whats wrong. The timing diagram I showed does not reflect the overlapping phase shift
each clock exhibits.

Each clock is phase shifted by 45 degrees, 50%duty cycle, so there is no simple inverted relationship between any two phases.

This is the output for the LUT encoding I used. Main criteria was 4 clocks, 50% duty cycle, phase shifted.

The clock phases are simple decode, not used as LUT fdfbk.

View attachment 204273

Regards, Dana.
Makes sense re our disagreement.

Now you have 8 states, which require only 3 registers. This implies you can encode all 8 states in 4 registers giving 4 outputs without any decoding.
 

Thread Starter

danadak

Joined Mar 10, 2018
4,057
Or I could use 2 LUTS, one with 3 regs to yield 8 states, the other no regs, just decode. 3 in, 4 out.

Regards, Dana.
 

joeyd999

Joined Jun 6, 2011
4,431
If the decode is clocked in sync all is good......otherwise raw decode = glitches.
I hate it when posts are edited after I reply to them.

Yes, as long as the decode is captured by clocked registers, you can avoid glitches.

You realize then, with two LUTs, the decoded output will always be delayed one clock behind your state counter.

Much easier to just encode the desired output as the state machine sequence, thereby avoiding all this messiness with glitches, clock skews, and extra registers.

As an alternative, you could encode the 3 bit state machine in Gray Code, as opposed to binary, and use straight combinatorial logic for glitchless decode.
 

Thread Starter

danadak

Joined Mar 10, 2018
4,057
I hate it when posts are edited after I reply to them.

Yes, as long as the decode is captured by clocked registers, you can avoid glitches.

You realize then, with two LUTs, the decoded output will always be delayed one clock behind your state counter.

Much easier to just encode the desired output as the state machine sequence, thereby avoiding all this messiness with glitches, clock skews, and extra registers.

As an alternative, you could encode the 3 bit state machine in Gray Code, as opposed to binary, and use straight combinatorial logic for glitchless decode.
Yes on the delay and 2 LUTs.

Its interesting reading this thread. Gray code is not exactly all that it seems when actually implemented
in silicon and state machines. Topic is pretty deep, I am beginning to think its amazing any digital logic
works :).

https://www.embeddedrelated.com/showthread/comp.arch.embedded/77650-5.php#tabs1-chronological


Regards, Dana.
 

andrewmm

Joined Feb 25, 2011
574
A quick look at your timing diagram,
what would you get with a three bit shift register, say shift right.
invert the output of the right most register, and feed it into the input of the left register.

then look at the waveform of each register, true and inverted output ,
 

Thread Starter

danadak

Joined Mar 10, 2018
4,057
Just for drill tried this -

1586977714315.png

It generated no glitches, even though its bad practice, LUT3 being non registered.

Used 500 Mhz 2 Gs/s scope to try and capture something. No problems found.


Did, as you pointed out, cut down chip logic fabric resources used from ~ 8% to 3%, significant in my book.


Then for drill Gray coded the reg LUT, LUT_2, same results, no glitches, as we would expect.


Regards, Dana.
 
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