PCB Voltage Withstand Capability

Thread Starter

TechWise

Joined Aug 24, 2018
143
I am looking for any standards or recommendations for how much voltage can safely be applied across adjacent layers on a 4 layer PCB. There's loads of material out there on safe clearances between tracks but I can't seem to find anything relating to different layers. In this application, I would like to have 800Vdc on filled plane on layer 2 and then route some traces at 0Vdc on layer 1 above. Note that this is for functional isolation only, not safety critical.

I'm awaiting a reply from my PCB manufacturer to see if I need to go down the custom stack-up route but I thought I'd ask here for general advice in the meantime. Does anyone have any useful links?
 

prairiemystic

Joined Jun 5, 2018
150
It all depends on the PCB laminate's FR-4 ratings as a solid insulator.
Cheap PCB laminate is mostly glue, not as much fiberglass - so it can vary between manufacturers.

Safety standards give acceptable voltage ratings, which I would follow even though it's supposedly functional insulation- if it arcs and carbon tracks, what prevents the PCB from burning up or the product from becoming unsafe?

The standard gives thickness requirement of 0.4mm for 300V, 0.6mm for 300-600V and 1.0mm for 600-1,000V.


61010_pcb_insulation.JPG
 

Thread Starter

TechWise

Joined Aug 24, 2018
143
It all depends on the PCB laminate's FR-4 ratings as a solid insulator.
Cheap PCB laminate is mostly glue, not as much fiberglass - so it can vary between manufacturers.

Safety standards give acceptable voltage ratings, which I would follow even though it's supposedly functional insulation- if it arcs and carbon tracks, what prevents the PCB from burning up or the product from becoming unsafe?

The standard gives thickness requirement of 0.4mm for 300V, 0.6mm for 300-600V and 1.0mm for 600-1,000V.


View attachment 223856
Wow, it looks like I need 1mm of prepreg then which is a lot. Definitely a custom stack-up job then.

There are two isolation barriers between the high voltage and the user - one if formed by the isolated gate drivers and an 8mm clearance gap under them, the second is formed by USB digital isolators with another 8mm gap. I take your point about a catastrophic failure potentially arcing over those though in a worst case scenario.
 

prairiemystic

Joined Jun 5, 2018
150
If an inner HV trace does not have something directly on top or below it, if the clearance can be 1mm diagonally then the thinner prepreg could be used.

800V is a lot, and the insulation spec is based on the voltage stress being there most of the time verses the material aging and partial discharges occurring. It has really nothing to do with the max. breakdown voltage rating of FR-4 which many people think is the guideline "The voltage break down of FR-4 is 20kV/mm" uh just try it lol.
You have to also consider high frequency pulses (dielectric heating), transient overvoltages that might be occuring, temperature etc., so the dielectric can last years. The stray capacitance you also don't want.

I think an 800VDC bus is pretty steady, but not the gate-drive for the upper bridge semi. That has HV, high frequency swings that really stress a dielectric. For HF square waves the standards have additional requirements beyond DC/mains AC.
 

Thread Starter

TechWise

Joined Aug 24, 2018
143
If an inner HV trace does not have something directly on top or below it, if the clearance can be 1mm diagonally then the thinner prepreg could be used.

800V is a lot, and the insulation spec is based on the voltage stress being there most of the time verses the material aging and partial discharges occurring. It has really nothing to do with the max. breakdown voltage rating of FR-4 which many people think is the guideline "The voltage break down of FR-4 is 20kV/mm" uh just try it lol.
You have to also consider high frequency pulses (dielectric heating), transient overvoltages that might be occuring, temperature etc., so the dielectric can last years. The stray capacitance you also don't want.

I think an 800VDC bus is pretty steady, but not the gate-drive for the upper bridge semi. That has HV, high frequency swings that really stress a dielectric. For HF square waves the standards have additional requirements beyond DC/mains AC.
Well the PCB manufacturer has just sent me the figure of 20kV/mm for their prepreg. Obviously that's not the whole story though as you've pointed out.

The application is a two-level SiC converter, so theres very fast di/dt and dv/dt going on. There's snubbers on the switches so transient overshoots should be at a minimum. In any event, if an overshoot exceeds 1200V then the MOSFETs are toast anyway. The 800V DC Link and DC GND are on layers 2 and 3 respectively, so they're well separated by the FR4 substrate in the middle. However, there are source and gate connections on the top layer which are routed over the 800V plane below, and they will swing from 0V to ~815 volts as the top switch turns on and off.

I don't think there should be too much heating going on. The heatsinks are oversized for the expected losses and all of the large current carrying traces are large pours of 2oz copper. I'm expecting a maximum of about 12.5A per conductor which should be easily acceptable for a 40mm wide copper pour only 50mm long.
 
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