Output clamp

Thread Starter

pingnu

Joined Sep 29, 2020
7
I am trying to clamp a signal on an existing circuit it does not appear to completely turn off the control P4_1 is only 3v3 IO signal.
For safety, I want to be able to clamp the output at pin7 is the device suitable 2N7002. I am only using it as I have a similar circuit using non inverting amplifier and 5v control line it does have a pull-up resistor for the gate.
 

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ericgibbs

Joined Jan 29, 2010
12,497
hi ping.
Welcome to AAC.
What voltage level do you want to clamp it too.?
Have you considered using a transistor clamp.?
E
 

Papabravo

Joined Feb 24, 2006
15,772
From the datasheet of the 2N7000, what is the Vgs(th) of the part?
Do you know what that value means in terms of the device operation?
 

Thread Starter

pingnu

Joined Sep 29, 2020
7
hi ping.
Welcome to AAC.
What voltage level do you want to clamp it too.?
Have you considered using a transistor clamp.?
E
Just realised the signal is inverted it is difficult to scope as it is under a daughter board so I assume I need to invert the 2N7000 and invert the gate drive somehow. At the moment it is clamping to the internal diode. I need to clamp to agnd perhaps I need to add a transisitor to drive the fet in the negative domain
 

Thread Starter

pingnu

Joined Sep 29, 2020
7
From the datasheet of the 2N7000, what is the Vgs(th) of the part?
Do you know what that value means in terms of the device operation?
Apparently it is the voltage at which the gate will turn on I know it is a bit close for this device as I am trying to use 3v3 but I am switching a very low current. Voltage from gate to source so perhaps I need to drive negative as I just realised it is inverted.
 

Thread Starter

pingnu

Joined Sep 29, 2020
7
hi,
What is the type of signal at the junction of the two 5ks?
E
zero to 7.5 volts going into amp so negative -3.75 t junction I can of course change the values 1k and 9k. It is a PID driving a high power power supply
It is a ramp perhaps 10ms up 10ms hold and 10ms fall but can be adjusted.
 

Papabravo

Joined Feb 24, 2006
15,772
Apparently it is the voltage at which the gate will turn on I know it is a bit close for this device as I am trying to use 3v3 but I am switching a very low current. Voltage from gate to source so perhaps I need to drive negative as I just realised it is inverted.
You missed an important word. Vgs(th) is the voltage at which the device BEGINS to turn on. The voltage at which the device is fully on, so that rds(on) is at or near it's minimum value is higher. You might be operating the device in it's linear region which is, generally speaking, bad for the device, especially if you keep it there for a protracted period. You need to investigate a better solution.
 

Audioguru again

Joined Oct 21, 2019
2,991
Apparently the Vgs(th) is the voltage at which the gate will turn on.
No, it is the gate-source voltage that it barely turns on or almost turns off. The datasheet shows the 2N7000 and 2N7002 turn on very well with a Vgs of 10V and turn on fairly well with a Vgs of 5V.
 

Thread Starter

pingnu

Joined Sep 29, 2020
7
No, it is the gate-source voltage that it barely turns on or almost turns off. The datasheet shows the 2N7000 and 2N7002 turn on very well with a Vgs of 10V and turn on fairly well with a Vgs of 5V.
It is a enhanced fet and as the voltage is negative the internal diode is holding the on state to 0.6volts. I will do what eric gibbs suggests I need a hack for now and a proper solution for next spin, I do zero the dac but for some reason, the spi interface fails about 3% of the time. I wonder if I need to terminate the spi bus as it ought to be reliable
 

BobaMosfet

Joined Jul 1, 2009
1,645
I am trying to clamp a signal on an existing circuit it does not appear to completely turn off the control P4_1 is only 3v3 IO signal.
For safety, I want to be able to clamp the output at pin7 is the device suitable 2N7002. I am only using it as I have a similar circuit using non inverting amplifier and 5v control line it does have a pull-up resistor for the gate.
If you want the output on pin 7 to go towards the reference pin (pin 5), you need a high-input on the inverting input. so the feedback loop will drive it towards the reference.
 
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