Hi everybody,
sorry for my English.

digital signal amplifier

I have a small FPGA board,
I have to perform isolation with ADuM260N but the maximum output current -10mA ~ + 10mA, so I have to use a switching output amp that allows to wait for an output current of 25mA ~ 50mA and a voltage 5v for HIGH Logic Level and 0 ~ 0.5 max for the LOW Logic level and a frequency of 18000Hz.
I do not want a circuit difficult to achieve, because I have 16 outputs, I want to do it if possible with a bipolar transistor and the output is not inverted.
so
What type of montage do you reconcile me?
which transistor to choose?

That's pretty much what I want to do.


thank you

 

I have to perform isolation

What do you mean by "isolation"?

a switching output amp that allows to wait for an output current of 25mA ~ 50mA and a voltage 5v for HIGH Logic Level and 0 ~ 0.5 max for the LOW Logic level and a frequency of 18000Hz.

So you want to go from a 0-3.3V signal to a 0-5V signal at 50mA maximum with no signal inversion, is that correct?

For that you could use an NPN-PNP driver stage, such as in the LTspice simulation below:

 

Thanks for your response Crutschow.

no I want to go from a 0-5V signal at 10mA maximum to a 0-5V signal at 50mA maximum without signal inversion.
because I use a digital isolator (ADuM260N) after the FPGA.

 

Unless I am mistaken, that is just what Crutschow designed and demonstrated. What is the difference between what he presented and what you need?

 

Hi DickCappels,
Not all goes well with that Crutschow, I just answered that question

So you want to go from a 0-3.3V signal to a 0-5V signal at 50mA maximum with no signal inversion, is that correct?

no I want to go from a 0-5V signal at 10mA maximum to a 0-5V signal at 50mA maximum without signal inversion.

again thank you for your help.

 

Hi DickCappels,
Not all goes well with that Crutschow, I just answered that question

So you want to go from a 0-3.3V signal to a 0-5V signal at 50mA maximum with no signal inversion, is that correct?

no I want to go from a 0-5V signal at 10mA maximum to a 0-5V signal at 50mA maximum without signal inversion.

again thank you for your help.

I think you'll find that, although his circuit was designed based on a 3.3V input, it also does exactly what you need with a 5V input equally well.

It will draw just over 1mA from the 5V input signal (well under your 10mA limit) and is probably capable of delivering at least 100mA at the output (just guessing on that figure, but it should be a conservative guess.)

 

I think you'll find that, although his circuit was designed based on a 3.3V input, it also does exactly what you need with a 5V input equally well.

It will draw just over 1mA from the 5V input signal (well under your 10mA limit) and is probably capable of delivering at least 100mA at the output (just guessing on that figure, but it should be a conservative guess.)

Oops! Sorry, I'm half asleep and misread/miscalculated a bit. Current draw from input will be closer to 1/10mA and he actually shows the output trace at around 50mA, assuming a 100 ohm load. Regardless, the point is that his circuit does what you want. If you had any doubts about the upper limit of output current capability, you could probably drop resistance of R2 and/or R3. I'm too sleepy to do the math, but his circuit is conceptually what you need, and may or may not benefit from some slight resistor value adjustments.

 

Personally I would not second-guess Crutschow's math. Notice that each transistor inverts the signal so the net result is amplification with the output being a non-inverted version of the input.

 

Personally I would not second-guess Crutschow's math. Notice that each transistor inverts the signal so the net result is amplification with the output being a non-inverted version of the input.

Agreed. I already knew he had the signal inversion correct (or rather, the lack thereof.) It was the current that intrigued me.

I see now what was tripping me up. I was reading the thread starter's intent as needing an output capable of at least 25-50mA, as opposed to needing one with a deliberate limit at 50mA. The way I had read it, you'd want saturated switch behavior (maybe assuming 10x current gain per transistor stage) and therefore probably lower resistor values.

I have no doubt that the circuit will perform as crutschow intended. The only thing I'm uncertain about is the original user requirements.

 

Hi ebeowulf17,
It is a system of synchronization for camera, encoder, laser ... the program has been written in the FPGA.
The problem is that all this is embedded in a vehicle and each equipment has its proopres characteristics and that there is a diiferant model and constructor. I want to make a universal input/output system for it's perephiric.
and not to try to revive the cercuit with every arrival of new equimement.

 

The circuit I posted will work fine with a 0-5V input.

If you can tolerate a 0.7V reduction in the 5V high signal (logic high output would be ≈4.3V), then you could just use an emitter follower at each output, consisting of a common NPN transistors, such as a 2N3904 or 2N2222.

 

Thank you for your help.