Hi everyone,


I'm a recent graduate and I've just started working on a project involving 4-20mA input and output signals. The system I’m working on has isolated grounds for the two circuits, and I'm trying to calibrate the readings of these inputs and outputs.


In my simulation, I’m focusing on the differential amplifier circuit, where I’m measuring the voltage/current difference across R5 and using the differential amplifier to reproduce this difference in the output. However, the simulation has been giving me some issues. At some point, it slows down, and the plot starts showing noise and disturbances.


I asked ChatGPT for help, and it pointed out that I might have a floating node. I solved the issue by inserting a nodeset command: nodeset V(com2)=0 V(v2#branch)=1. When I run the simulation with the .op command, everything works fine without any problems.


My question is: is the circuit I designed fundamentally wrong, or can it work with the right precautions and adjustments? I’d appreciate any insights or suggestions on this!

 

I ran the simulation okay (below), even without the nodeset command, and saw no obvious problems with it.

Note that the .op (DC op pnt) simulation command gives a single trace over the stepped values of R.

 

I ran the simulation okay (below), even without the nodeset command, and saw no obvious problems with it.

Note that the .op (DC op pnt) simulation command gives a single trace over the stepped values of R.

View attachment 344378

I updated the attached file because it was the wrong one. Try again; the version is 4.1.1.
Then, run the .tran, not the .op, and you will get this result.
Let me know if it's more accurate to run the .op instead of the .tran, which is closer to reality?

 

hi frank,
Adding this .options cmd I see this.
E

 

if it's more accurate to run the .op instead of the .tran, which is closer to reality?

The .op give a nice single trace over the stepped values, but doesn't include any transient effects or possibly instabilities in the circuit.

For that you can run the .tran sim with a stepped voltage input at U2.
The output should not show any significant overshoot or ringing for the step.

 

hi frank,
Have you considered this method?

E

 

Your concept of an isolated ground being primarily inductive is suspect. It very low impedance at DC which does not reflect reality IMHO. Don't you want something like a high resistance in parallel with a capacitor that provides and AC ground at high frequencies. High frequencies with respect to whatever you imagine in your measurement régime.

 

I ran a transient response with a stepped input to U2, and the output exhibited high frequency oscillations (which is what you saw in your post #3 simulation).
The problem is the transistor Q2 at U2's output increases the open loop gain and thus the op amp is no longer compensated for stable operation with negative feedback to it's plus input.
The circuit will need additional compensation, or a different feedback configuration to prevent the oscillation.

One possibility is to change Q2 to a PNP and operate as an emitter-follower with the collector to common and the emitter to R5, to amplify current but not voltage, which thus will not increase the loop gain.
For that the input feedback connections to U2 must also be inverted.

 

Hi C,
Agreed, the system is not stable.
E

 

I ran a transient response with a stepped input to U2, and the output exhibited high frequency oscillations (which is what you saw in your post #3 simulation).
The problem is the transistor Q2 at U2's output increases the open loop gain and thus the op amp is no longer compensated for stable operation with negative feedback to it's plus input.
The circuit will need additional compensation, or a different feedback configuration to prevent the oscillation.

One possibility is to change Q2 to a PNP and operate as an emitter-follower with the collector to common and the emitter to R5, to amplify current but not voltage, which thus will not increase the loop gain.
For that the input feedback connections to U2 must also be inverted.

The circuit section highlighted in the box represents the output stage of the 4-20mA loop, but it does not fully reflect reality. For simulation purposes, I designed an equivalent circuit that operates similarly to the real one, where current regulation is managed by an N-MOS instead of Q2, driven by an op-amp controlled by a DAC via SPI.

Now, I’d like to ask if the issues in the simulation caused by this circuit can be ignored, given that it does not accurately reflect the real one and is different, or if the problems I’m experiencing in the simulation will also occur in reality.

 

I’d like to ask if the issues in the simulation caused by this circuit can be ignored, given that it does not accurately reflect the real one and is different, or if the problems I’m experiencing in the simulation will also occur in reality.

Depends upon the feedback loop of the real circuit, and can't know that without seeing its schematic.

If it's just a matter of substituting an N-MOSFET for the NPN, then there could be a real problem.
In that case, changing to a P-MOSFET connected as a source-follower (source to R5) should give a stable circuit (example below):