(not so) Simple opto-coupler/MOSFET question :)

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
No pull up or pull down resistor can compare to the speed of a Gate Driver, so they don't need the resistors.

K thanks I'll remove them then. One problem I have encountered though is I need pin 2 on the driver to be pulled down by the activation of optos 1 and 3 (descending) thereby activating the P-channels. In this configuration it isn't achieving that in sim. I know the sim isn't exactly accurate but it continues to show no voltage change at pin 2 when the corresponding opto is activated. It isn't a library component and pin potentials aren't changing at all with opto activation (p or n channel control) so I do think I can rely on the simulation at all after the AND gates.

NOTE on the first driver pins 3 and 4 are not supposed to be joined that's an error
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
Oops. I thought you were talking about the outputs. :oops:
Yeah I was no worries :D

I bought up the inputs as it just came up then. If I can't pull down the potential at pin 2 input then I think I'm going to be forced to use an inverted output driver for the P-channel control.
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
I found some inverted and non-inverted logic 1.5A dual drivers TC4426+TC4427 respectively and I've applied them. I think it might be easier as the logic was originally designed for a N-channel only system. Only worry now is am I exceeding the 1Amp available to me on the signal generation side? What do you think, this may be easier?

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ronv

Joined Nov 12, 2008
3,770
You will need pull downs on the opto outputs. If you need an inversion you can either move the opto diode to the emitter side of the transistor or add a resistor to the collector of it's output and use that to drive the chip. The emitter would then go to ground.
What is the purpose of the 2 FETs that go to ground?
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
You will need pull downs on the opto outputs. If you need an inversion you can either move the opto diode to the emitter side of the transistor or add a resistor to the collector of it's output and use that to drive the chip. The emitter would then go to ground.
What is the purpose of the 2 FETs that go to ground?
I needed to switch the polarity across the load to create the modified sine wave so the P-channels allow current to flow to the load and the N-channels allow it flow to ground. I originally intended to use N-channels for both purposes but I would need a driver with some kind of voltage boost for the gate at the point of current entry to the load, the cheaper solution was to use parallel P-channels to overcome the inherent problem of GS threshold voltage optimisation.

The newest diagram uses inverted and non-inverted drivers which I am hoping will negate the need for me to add any pull up/down resistors at all now. The datasheet for the drivers gave me the impression all that is integrated. But you recommend putting some on the opto output- driver interface? The other worry now is that the opto-couplers are no longer actually isolating the circuit and I can't run them off the 12V rail as its too high for the driver input, is this actually anything to worry about? Do I need optos anymore?
 
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ronv

Joined Nov 12, 2008
3,770
Seems like you have some extra FETs, but my poor old eyes have trouble with the schematic. :(
Google H - Bridge.
Yes, I see your point. The isolation between the 5 volt stuff and the 12 volt stuff is lost so if something goes wrong a lot of stuff could go up in smoke. The driver would probably protect the other stuff, but there is no guarantee. You definitely deed a pull down on the output transistor of the opto.
I see now why someone had you add the diode to the 7805. There is a diode in the output of it. I would get rid of that one too. If it is reverse protection you are after put the diode on the input to the regulator.
You can get rid of the optos, but these high power circuits blow up a lot during debug. :eek:
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
I think I see now. The and gates make sure everyone is off for a clock period. Is that correct?
Yeah that's exactly it :) Gates 1 and 4 activate then OFF then 2 and 3 then OFF and repeat. It is basically a really poorly illustrated H-bridge lol sorry not my best design.
I would ideally like to find some way to isolate the signal generator from the switching components is there anyway you can think of that would allow me to do that or is my driver basically now my isolator? The 12V rail can draw a maximum of 30-40A I really would like that separate lol.
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
Does it look like this except parallel FETs?
Yeah that's basically the design I worked from I just split it down the middle vertically and rotated one side 180 and used sets of parallel P-FETS. :)
The only real reason I did a more linear layout was so I could visualise the layout of the bus bars for higher supply.

Those Driver optocouplers look perfect, thank you very much. I could do with one that has two independent inputs and outputs. I'll get looking now I'm sure I'll find something fitting :D
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
I had a look at those gate driver output optocouplers but I can't use them in this application unfortunately as they have a maximum operating frequency of 50kHz, I would require 4 of them for control and there is no inverted output version. Dam I don't think I'm going to be able to isolate those drivers :(
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
I guess this is always an option, a second 5V regulated rail for driver feeds. I was concerned about using the maximum current draw of the first regulator anyway so I guess it could work. This way the signal speed bottle neck would be the optos with a cut-off frequency of 250kHz.

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Thread Starter

Marcus2012

Joined Feb 22, 2015
425
Do you know if it matters if the GS voltage is above (or below in the case of P-channels) that of the stated threshold voltage? Would that damage the transistors?
 

#12

Joined Nov 30, 2010
18,224
See post #6. "The threshold voltage is the beginning of conduction, not the end. Every mosfet I know would be happy with 12 volts on its gate."

Read the datasheet! The graphs will tell you the performance and parameters of the chip.
 

Thread Starter

Marcus2012

Joined Feb 22, 2015
425
See post #6. "The threshold voltage is the beginning of conduction, not the end. Every mosfet I know would be happy with 12 volts on its gate."

Read the datasheet! The graphs will tell you the performance and parameters of the chip.
Thanks I looked back thinking this had been answered, I'm going blind it seems, sorry
 

ronv

Joined Nov 12, 2008
3,770
What are you driving with such a high frequency?
The one I linked is quite a bit faster than the one you have. Check the rise and fall times.
I'll get back with how to invert it.
 
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Thread Starter

Marcus2012

Joined Feb 22, 2015
425
Right so I've had to use the Gate driver optocouplers to isolate this circuit efficiently. As no gate driver optocoupler I can find has inverted output I have to leave the P-channel MOSFETs's drivers (drivers 1 and 3 descending on diagram) ON by default to close the P-channel. So to activate the Ps I need to pull the input (anode, pin 2) down low using the activation of AND gates 1 and 3 (again descending) and their corresponding NPNs. I have tried adding these pull down resistors (R8+13) but I don't think it's quite working. Have I got these in the wrong place?

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Thread Starter

Marcus2012

Joined Feb 22, 2015
425
What are you driving with such a high frequency?
The one I linked is quite a bit faster than the one you have. Check the rise and fall times.
I'll get back with how to invert it.
Induction system. I'm still working on the LC circuit for that but that's a whole different problem lolz.

Yeah was tired when I read that I think the ones you linked were perfect I just misread it. These ones are 4A but a bit cheaper. :D
 
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