Need HELP with PLL Design

Thread Starter

Dhruvajit

Joined Aug 9, 2020
2
Hello! I have made a PLL design which has an input frequency of 5Mhz and requires an output of 40MHz. Basically the feedback path of the PLL will have to be frequency multiplier of 8.

MY individual blocks of PLL such as PFD, Charge Pump, VCO and frequency divider are working! I have checked them thoroughly. Could anyone help me out who has had previous experience with making a PLL?

I have individually made each and every block with PMOS and NMOS using 180nm technology! I am attaching picture of the graph and circuit if it helps! I suppose there is an issue with the loop filter can anybody help?

1596983567536.png

1596983600775.png
 

andrewmm

Joined Feb 25, 2011
526
You say you have checked all the parts.
why is C1 floating ?

Way to look a this is chose an outputs point and work backwards , do the wave forms seem like you would expect for the input that section is getting ?

BYW. Please, do not get into the habit of putting ground on top of a symbol, it makes reading more difficult with is not your aim,
 

Thread Starter

Dhruvajit

Joined Aug 9, 2020
2
You say you have checked all the parts.
why is C1 floating ?

Way to look a this is chose an outputs point and work backwards , do the wave forms seem like you would expect for the input that section is getting ?

BYW. Please, do not get into the habit of putting ground on top of a symbol, it makes reading more difficult with is not your aim,
Hello Sir! I uploaded the wrong picture of the circuit. The circuit is right now like this
1596986273746.png
 
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