Thank you for your detailed feedback. I truly appreciate the time you took to analyze my design.


Regarding the primary inductance (Lm):

• My design is intentionally DCM (Discontinuous Conduction Mode) at 100 kHz with 60 W output, operating from a universal AC input (85–265 VAC).
• Under these conditions, the calculated inductance comes out to approximately 82 µH, which matches the energy-based formula:
• Lm = (Vdcmin * Dmax)^2 / (2 * Pin * fs)
  
  Lm = (71.27 * 0.47698)^2 / (2 * 70.6 * 100000)
  Lm ≈ 81.8 uH
  
  
• resulting in 81.8 µH.

Your 733 µH estimation seems to assume a CCM (Continuous Conduction Mode) design with a different Ton and peak current profile, which would naturally require a much larger magnetizing inductance.


I agree with your other points:

• Sandwich winding is an excellent idea to reduce leakage.
• Compensation should be carefully reviewed to avoid excess phase shift – I will analyze my feedback loop again to ensure stability.

Thank you once again for the valuable input!

And NOW you mention 85Volt operation, but you have calculated it for 71V. Designing for “universal” input is quite a compromise in efficiency, if you intend to use it on a 230V supply.

 

Personally I'd junk all that compensation around the TL431 and the 100nF on the emitter of the opto-coupler. It actually seems to have a detrimental effect. CAVEAT: simulations are not real-life, but they should give a fair imitation....

Here's how it looks 'naked': ripple on the 12v at 5A is 60mV. NB I had to change the timing capacitor C9 to get it to run at 100kHz - not looked into why...




And with the extra baggage - just the 100nF on the left (275mV ripple), just on the TL431 in the middle (110mV ripple), and with both on the right (962mV ripple)

 

Personally I'd junk all that compensation around the TL431 and the 100nF on the emitter of the opto-coupler. It actually seems to have a detrimental effect. CAVEAT: simulations are not real-life, but they should give a fair imitation....

Here's how it looks 'naked': ripple on the 12v at 5A is 60mV. NB I had to change the timing capacitor C9 to get it to run at 100kHz - not looked into why...

View attachment 355170


And with the extra baggage - just the 100nF on the left (275mV ripple), just on the TL431 in the middle (110mV ripple), and with both on the right (962mV ripple)

View attachment 355171

First of all, I can’t thank you enough for all your efforts. I will follow your recommendations for production. I don’t mean to sound presumptuous, but I believe you used the UC3844 in the simulation, while my schematic was based on the UC3842. Since the UC3844 operates at 50% duty cycle, you changed capacitor C9. You mentioned you hadn’t looked into the reason, so I just wanted to point that out.


These simulations seem to align very well with the calculations on my design page.


I’m not very knowledgeable about simulation, and I’m still learning electronics. I focused on understanding the theoretical calculations and created a design from there. If you could tell me the name of the application you’re using, I would truly love to learn it as well.


Most importantly, I want you to know how deeply grateful I am for the time you have dedicated to me. Time is the most precious thing a person can give, and I will never forget the generosity and patience you’ve shown throughout this process. Thank you – sincerely – for sharing not only your knowledge but also your valuable time.

 

Personally I'd junk all that compensation around the TL431 and the 100nF on the emitter of the opto-coupler. It actually seems to have a detrimental effect. CAVEAT: simulations are not real-life, but they should give a fair imitation....

Here's how it looks 'naked': ripple on the 12v at 5A is 60mV. NB I had to change the timing capacitor C9 to get it to run at 100kHz - not looked into why...

View attachment 355170


And with the extra baggage - just the 100nF on the left (275mV ripple), just on the TL431 in the middle (110mV ripple), and with both on the right (962mV ripple)

View attachment 355171

Looks like you have some sub-harmonic oscillations going on there, which are probably due to instability in the error amplifier. If it were a valve amp, we'd call it "squegging".
There are definitely too many phase shifts in the feedback loop but I'd say that the TL431 needs its dual slope compensation, and the compensation should be removed from the UC3842, except perhaps a very small capacitor across the opto. Connecting the opto to the COMP pin is essential if it is going to behave. Putting the signal through the UC3842's error amplifier after it has already been through a TL431 error amplifier is asking for trouble.

 

Looks like you have some sub-harmonic oscillations going on there, which are probably due to instability in the error amplifier. If it were a valve amp, we'd call it "squegging".
There are definitely too many phase shifts in the feedback loop but I'd say that the TL431 needs its dual slope compensation, and the compensation should be removed from the UC3842, except perhaps a very small capacitor across the opto. Connecting the opto to the COMP pin is essential if it is going to behave. Putting the signal through the UC3842's error amplifier after it has already been through a TL431 error amplifier is asking for trouble.

Based on both Mr. Irving's feedback and yours, I can see that this approach makes much more sense. Would you agree?

 

Based on both Mr. Irving's feedback and yours, I can see that this approach makes much more sense. Would you agree?

View attachment 355176

No, that will oscillate. You need hf compensation from cathode to adj. Here's the paper I linked to back in post 18.

 

No, that will oscillate. You need hf compensation from cathode to adj. Here's the paper I linked to back in post 18.

Thank you very much. I will review the document and make the necessary corrections. Thank you very much for your interest.

 

Thank you very much. I will review the document and make the necessary corrections. Thank you very much for your interest.

I've read a lot about switched-modes and their error amplifiers, and SLUP340 is by far the easiest to understand. If you have done audio amplifiers, the principles are the same.

 

Looks like you have some sub-harmonic oscillations going on there, which are probably due to instability in the error amplifier. If it were a valve amp, we'd call it "squegging".
There are definitely too many phase shifts in the feedback loop but I'd say that the TL431 needs its dual slope compensation, and the compensation should be removed from the UC3842, except perhaps a very small capacitor across the opto. Connecting the opto to the COMP pin is essential if it is going to behave. Putting the signal through the UC3842's error amplifier after it has already been through a TL431 error amplifier is asking for trouble.

As an avid amateur radio enthusiast in my youth I'm well aware of squegging , not just in valve amps!

There's various things going on there, possibly related to the MOSFET model which includes inductances for the pins. I've not investigated it in detail.

However, while I agree that too many compensations can cause instability, all the application notes (TI, SGS, ST, et al) use compensation around the error amp, in different configurations depending on CCM v DCM, and current mode v voltage mode feedback. Not one shows secondary side compensation. I'm not saying it can't be done that way, but there's no manufacturer recommended approach to that. However onsemi have this design guide to TL431 compensation that may be helpful, but this is quite advanced stuff.

This document also gives extensive info on TL431 use.

 

As an avid amateur radio enthusiast in my youth I'm well aware of squegging , not just in valve amps!

There's various things going on there, possibly related to the MOSFET model which includes inductances for the pins. I've not investigated it in detail.

However, while I agree that too many compensations can cause instability, all the application notes (TI, SGS, ST, et al) use compensation around the error amp, in different configurations depending on CCM v DCM, and current mode v voltage mode feedback. Not one shows secondary side compensation. I'm not saying it can't be done that way, but there's no manufacturer recommended approach to that. However onsemi have this design guide to TL431 compensation that may be helpful, but this is quite advanced stuff.

This document also gives extensive info on TL431 use.

The most common circuit shown is a dual-slope compensation, with one capacitor between cathode and adj to give one slope and a capacitor across the opto to give the second.
The problem with the UC3842 is that it was originally designed for non-isolated supplies, so comes with a built-in error amplifier, where it is not needed. More modern device designed for isolated supplies have no error amplifier, and the designer generally uses the TL431.
Once the TL431 has been designed in, the problem is what to do with the UC3842's error amplifier. The obvious answer is to couple the feedback opto into the feedback pin, but that allows the opto to add another 90° of phase shift.
The 3842 was designed with a current-limited output on the error amplifier so that it could be compensated by a single capacitor to ground, and that current limit can be put to good use when the error amplifier is not required to provide a load for the opto, so that the output of the opto can be coupled to the current comparator without adding extra phase shift.

 

The most common circuit shown is a dual-slope compensation, with one capacitor between cathode and adj to give one slope and a capacitor across the opto to give the second.
The problem with the UC3842 is that it was originally designed for non-isolated supplies, so comes with a built-in error amplifier, where it is not needed. More modern device designed for isolated supplies have no error amplifier, and the designer generally uses the TL431.
Once the TL431 has been designed in, the problem is what to do with the UC3842's error amplifier. The obvious answer is to couple the feedback opto into the feedback pin, but that allows the opto to add another 90° of phase shift.
The 3842 was designed with a current-limited output on the error amplifier so that it could be compensated by a single capacitor to ground, and that current limit can be put to good use when the error amplifier is not required to provide a load for the opto, so that the output of the opto can be coupled to the current comparator without adding extra phase shift.

Ah, thanks for that explanation, it makes sense. I've not used that device in anger, mostly I've used the TNYxxx for <30W AC/DC. What would your recommended device for an isolated supply of this nature?

 

Ah, thanks for that explanation, it makes sense. I've not used that device in anger, mostly I've used the TNYxxx for <30W AC/DC. What would your recommended device for an isolated supply of this nature?

A while since I last made one! The last one was, I think, using an ON-Semi NCP1216. If you look at the internal circuit diagram in the datasheet, you can see that it is very much a UC3842 minus the error amplifier. The FB pin connects to exactly where the COMP does in the UC3842, and is provided with 20k pull-up resistor instead of the constant current source that the COMP output provides in the UC3842.
ONe of the main problems with the 3842 is the amount of current it uses, especially as it lacks a low-power start-up mode, so the supply is left with a 2W dropper resistor that is permanently in circuit, which is obviously a bigger problem than if it were being designed for a 120V supply. The NCP1216 has a built-in startup circuit which switches off when the auxiliary supply can power the IC.

 

The last one was, I think, using an ON-Semi NCP1216.

Only issue is the NCP1216 is obsolete/no longer manufactured/no longer stocked at all the usual suspects except Digikey who have limited stock of the 133kHz/46%DC and 100kHz/75%DC parts. The NCP1239, NCP12400 and the more expensive TI UCC2863x series are all current and active, pin compatible and have greater functionality (fault detection, over-voltage, etc.).

@Bora Fikret Karakütük Since all of these require a minor pin change from the UC384x and you have to re-lay out the PCB anyway, I recommend you should upgrade your design to one of these.

 

Only issue is the NCP1216 is obsolete/no longer manufactured/no longer stocked

These devices evolve faster than the Covid virus!

 

Only issue is the NCP1216 is obsolete/no longer manufactured/no longer stocked at all the usual suspects except Digikey who have limited stock of the 133kHz/46%DC and 100kHz/75%DC parts. The NCP1239, NCP12400 and the more expensive TI UCC2863x series are all current and active, pin compatible and have greater functionality (fault detection, over-voltage, etc.).

@Bora Fikret Karakütük Since all of these require a minor pin change from the UC384x and you have to re-lay out the PCB anyway, I recommend you should upgrade your design to one of these.

Hello, first of all, thank you very much for your advice. I will definitely take it into account in my next SMPS design. Following your previous recommendations, I focused more on the compensation part, and after reading a few additional technical documents, I came to the conclusion that my earlier design had several inaccuracies. Your guidance was very important in helping me reach this understanding.

The technical document I prepared, along with the corrections I made afterwards, are summarized below, and I believe I was able to achieve a much more stable design. I realize I’ve taken up quite a bit of your time, but I would greatly appreciate it if you could review it. The related calculations are in step 12 of the document. The document is not in English, but at least you can check my calculations.

Thank you again for all your efforts.

 

On a UC384x I would never connect an opto to the FB input. I would always connect to COMP.

One thing to note (probably for future improvements): 200mT does not necessarily give the best efficiency. Sometimes the lowest losses are at a lower flux density.

 

Well that change certainly improves things: No squegging and 12v ripple is around 15mV p-p.



However, you might want to reconsider those time constants in the loop as the step response from no load -> full load and back is not great (LH picture)... Reducing C8 and C18 from 10n to 1n improves the step response (RH picture) with no obvious impact on stability.. To me this suggests there is over-compensation. You need to be nearer the point of instability to get a fast step response, without going too far of course. This comes back to @Ian0 's comment about having only 1 point of compensation.

 

Well that change certainly improves things: No squegging and 12v ripple is around 15mV p-p.

View attachment 355359

However, you might want to reconsider those time constants in the loop as the step response from no load -> full load and back is not great (LH picture)... Reducing C8 and C18 from 10n to 1n improves the step response (RH picture) with no obvious impact on stability.. To me this suggests there is over-compensation. You need to be nearer the point of instability to get a fast step response, without going too far of course. This comes back to @Ian0 's comment about having only 1 point of compensation.

View attachment 355357View attachment 355360

Thank you very much for your help, your simulation results were really useful. I tried to recreate the circuit in LTspice, but I couldn’t get it to work properly. Would it be possible for you to share the .asc file? If you used any custom models (.lib or .subckt files), I would really appreciate it if you could also let me know. I’m attaching my own (probably wrong) .asc attempt below, in case you can point out what I did wrong. Thanks again for your support!”

 

The problem is, like many, you've designed your schematic, and while drawing you've wanted an NMOS MOSFET. So you logically pick the NMOS MOSFET symbol at the top of the list (even though it says its for spice simulation); how do I know this - because the pins are labelled D,G,S and not 1, 2, 3. If you'd picked the one lower down, Q_NMOS_GDS you'd have been fine. Unfortunately the default pin numbering for the 1st symbol is 1=D, 2=G, 3=S, which is true for many low-power MOSFETs but never for a power package such as TO-220, TO-247, etc where the centre pin and the tab is always the drain. ie 1=G, 2=D, 3=S. So when you attached the TO-220 footprint to the symbol, boom! See illustration below. As a learning exercise, this is the hard way - always check the the pin numbering in the footprint and cross-check with the datasheet - and then check it again a few days later... I wouldn't hold out too much hope for the controller chip either...

solid advice there... many have eventually run into same or similar situation.

 

solid advice there... many have eventually run into same or similar situation.

It's worse with SOT23 transistors, as it's not completely obvious which pin IS pin 3.