Hello,
I am studying digital electronics and I am a bit confused about the saturation conditions of the bjt.
I knew that the bjt saturates when the Vce is close to 0 and Vbe >= 0.7. However, when I was reading about TTL I got confused.
Can someone give me some intuition and explain me why in the case where both inputs are high, why Q2 and Q4 saturate and Q3 is OFF please.

I believe I understand something wrong because I cannot see how the saturation conditions are met.
If there is a more intuitive way to think about this please let me know.
Thank you

You have interchanged the "dependent" and "Independent" terms.

the bjt saturates when the Vce is close to 0 and Vbe >= 0.7 is not correct.

it should be when the bjt saturates, the Vce is close to 0 and Vbe >= 0.7

 

Technically, it's the forward biasing of the CB junction, while the BE junction is forward biased, that defines saturation mode.

 

You have interchanged the "dependent" and "Independent" terms.

the bjt saturates when the Vce is close to 0 and Vbe >= 0.7 is not correct.

it should be when the bjt saturates, the Vce is close to 0 and Vbe >= 0.7

Thank you

 

hi pj,
Please post calculations/work, so that we can check it.
E

 

Think of the Q2 as a super-ß transistor or as a darlington . . . when the both inputs are high
The d/s for such device (the TTL , SN74x00) specifies the output-high (sourced) current and the output-low (sank) current to differ by the factor of 10x - so there is some little difference compared to an OC (open collector) operation

 

Think of the Q2 as a super-ß transistor or as a darlington . . . when the both inputs are high

Why do that?
It just confuses the picture

 

Re crutschow's post#25. Using a darlington transistor for Q2 would require a modification to the circuit to take into account the higher saturation voltage of the darlington transistor.

Les.

 

Simulation