Hello,
I am studying digital electronics and I am a bit confused about the saturation conditions of the bjt.
I knew that the bjt saturates when the Vce is close to 0 and Vbe >= 0.7. However, when I was reading about TTL I got confused.
Can someone give me some intuition and explain me why in the case where both inputs are high, why Q2 and Q4 saturate and Q3 is OFF please.
I believe I understand something wrong because I cannot see how the saturation conditions are met.
If there is a more intuitive way to think about this please let me know.
Thank you
I am studying digital electronics and I am a bit confused about the saturation conditions of the bjt.
I knew that the bjt saturates when the Vce is close to 0 and Vbe >= 0.7. However, when I was reading about TTL I got confused.
Can someone give me some intuition and explain me why in the case where both inputs are high, why Q2 and Q4 saturate and Q3 is OFF please.
I believe I understand something wrong because I cannot see how the saturation conditions are met.
If there is a more intuitive way to think about this please let me know.
Thank you
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