Mux 4x1 and top problem

First of all, my english sucks.
i've basically begun to study vhdl today so i'm really new to all these

I'm trying to do a mux 4x1 and so far i got this:
library IEEE;
use IEEE.Std_Logic_1164.all;
entity MUX is
port (F1: in std_logic;
F2:in std_logic;
F3: in std_logic;
S: in std_logic_vector(16 downto 15);
F: out std_logic
);
end MUX;
architecture estr_mux of MUX is
begin
F <= F1 when S = "00" else
F2 when S = "01" else
F3 when S = "10" else
'0' ;
end estr_mux;

this part as i see is compiling but for some reason my top got a problem with it. Every time i try to run simulation i got this error
** Fatal: (vsim-3817) Port "F1" of entity "mux" is not in the component being instantiated.
# Time: 0 ps Iteration: 0 Instance: /topviado/L3 File: C:/altera/15.1/PJ1/MUX Line: 4