MOSFETs: Slowing down the switching speeds.

Thread Starter

Abbas_BrainAlive

Joined Feb 21, 2018
113
Hi there.

I was reading about different techniques employed in controlling load-switches. I came across a technical article by On Semiconductors, here. On page 4, it has the following down the switching speed of the load-switches.
Untitled.png

I am having some difficulty understanding how C1 is actually working, here. If the purpose of using C1 is to slow down the switching speed, thereby limiting the inrush current, why is it connected between the Gate and the Source? Shouldn't it be connected between the Gate and the GND?


Could anyone please help me in having a clear understanding of this?

I would really appreciate that.
 

crutschow

Joined Mar 14, 2008
27,004
C1 is not connected to the source, it's connected to the drain.
That connections acts as a Miller integrator to slow the MOSFET turn-on.

Below is the LTspice simulation of the circuit for example capacitor values of 1pf (bottom blue trace, minimum rise-time) and 50nF (bottom yellow trace).
You can see how the 50nF slows the rise-time.

upload_2019-4-2_0-56-43.png
 

ericgibbs

Joined Jan 29, 2010
12,498
hi AB.
Basically C1 provides negative feedback between Drain and Gate.

Consider that EN lis Low, Q1 is OFF, so the Gate of Q2 is zero volts wrt its Source ie: it is not conducting. So Vout will be zero volts.

If EN goes High and Q1 conducts the Gate of Q2 will be pulled Low wrt to its Source and will start conducting. so +Vout will rise will rise.
This rise in Vout will drive Q2 Gate more positive via C1.ie: negative feedback, so its conduction will reduce.

The same opposite effect will occur as EN goes Low. the negative voltage fall of Vout, via C1 will keep Q2 in conduction a little longer.


E
 

Thread Starter

Abbas_BrainAlive

Joined Feb 21, 2018
113
hi AB.
Basically C1 provides negative feedback between Drain and Gate.

Consider that EN lis Low, Q1 is OFF, so the Gate of Q2 is zero volts wrt its Source ie: it is not conducting. So Vout will be zero volts.

If EN goes High and Q1 conducts the Gate of Q2 will be pulled Low wrt to its Source and will start conducting. so +Vout will rise will rise.
This rise in Vout will drive Q2 Gate more positive via C1.ie: negative feedback, so its conduction will reduce.

The same opposite effect will occur as EN goes Low. the negative voltage fall of Vout, via C1 will keep Q2 in conduction a little longer.


E

Thanks a lot, ericgibbs.

Yeah, it's pretty simple!
It's silly I missed it!
 

danadak

Joined Mar 10, 2018
4,057
Also in the sim pay attention to the constrained current available
to change the Cg-d (and external C) in light of the 10K in series with
2N7000. The other direction 100K.

Regards, Dana.
 

Thread Starter

Abbas_BrainAlive

Joined Feb 21, 2018
113
Also in the sim pay attention to the constrained current available
to change the Cg-d (and external C) in light of the 10K in series with
2N7000. The other direction 100K.

Regards, Dana.
Thats the very purpose of using the gate-series resistor!
Or, are you trying to convey something else that I am missing?
 

danadak

Joined Mar 10, 2018
4,057
The idea that result of miller effect is compounded by not just C,
also affected by available current to change gate V. Stated another
way if I drive gate with a V source miller becomes irrelevant.

upload_2019-4-2_9-43-35.png


Regards, Dana.
 

ian field

Joined Oct 27, 2012
6,539
C1 is not connected to the source, it's connected to the drain.
That connections acts as a Miller integrator to slow the MOSFET turn-on.

Below is the LTspice simulation of the circuit for example capacitor values of 1pf (bottom blue trace, minimum rise-time) and 50nF (bottom yellow trace).
You can see how the 50nF slows the rise-time.

View attachment 173930
Not only that - the drain voltage will try to pull the gate up till the capacitor is charged. There will be a pulse of current when the power source is first connected. Only short and probably won't do damage - but it could freak any sequential logic downstream.
 
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