Something's certainly odd. There's 200mA base current!

I guess that is going to 0V via the forward biased base collector junction.

 

Dana,
Could you elaborate briefly on that with a simple schematic?
Curious / interested.
Thanks

This might be of use.

https://www.researchgate.net/post/W...or_and_emitter_of_an_NPN_Transistor_inversely


Regards, Dana.

 

Your gate drive circuit has 2 NPN transistors - one with it's collector grounded?

This configuration is incorrect, It can never drive the gate LOW.

I changed it to pnp....But still mosfets are getting shorted. very quietly. the supply 24 V goes to 20 the 16 ,..9 and then 0V heating up the smps.

 

I changed the sim to use a 2N3906 (PNP) for the bottom transistor and it works much better.
I don't like the fact that the top MOSFET has no DC path for the gate. It works OK in the sim but would probably not in a real circuit.

I too changed it to pnp, but the circuits not working still. what do you mean when you say top mosfet has no dc path for gate? which software are you using for simulation...

 

I would start by looking at gate drive with a scope, replace MOSFETs with
equivalent gate C, sure looks like you experiencing either excessive Vgs or
Vgd or Id due to overlap eg. both top and bottom mosfets shorting supply
rail.

You could do a single pulse (leaving MOSFETs in place) and set scope up for
single shot trigger.

https://hackaday.io/project/3176-gator-quad/log/11741-pwm-control-and-dead-time-insertion


Regards, Dana.

Thank you for your input.

I too feel the same. But if overlap is the problem, then it should not work on no load either.

How can I obtain a single shot trigger?

 

What is the purpose of the Zener diode and capacitor in parallel?

 

Thank you for your input.

I too feel the same. But if overlap is the problem, then it should not work on no load either.

How can I obtain a single shot trigger?

Scope should have a sweep mode single shot. You set Vtrigger for some value you are
looking for , like its max Vds spec value, and see if it gives you a trigger. Or you can take the
trigger out signal on scope, and use that to trigger the gate drive signal by pressing the run/stop
button on scope. So hitting the R/S button scope generates a sweep and a leading edge trigger
and you see a single sweep event, usually if there is a fault you can keep from blowing fets doing
it this way. Its tricky.

Regards, Dana.

 

Scope should have a sweep mode single shot. You set Vtrigger for some value you are
looking for , like its max Vds spec value, and see if it gives you a trigger. Or you can take the
trigger out signal on scope, and use that to trigger the gate drive signal by pressing the run/stop
button on scope. So hitting the R/S button scope generates a sweep and a leading edge trigger
and you see a single sweep event, usually if there is a fault you can keep from blowing fets doing
it this way. Its tricky.

Regards, Dana.

Thank you
Can you tell me which software is suitable for simulation of power circuits?

 

Can you tell me which software is suitable for simulation of power circuits?

LTspice. Freeware from Analog Devices.

 

LTspice. Freeware from Analog Devices.

thank you

 

I did a simulation of this, using 2N3904, but the emitter of the lower transistor doesn't get above 43mV despite 84mA flowing in the 51Ω resistor. I think this must be that the model doesn't understand 2N3904 with reverse polarity?

Sir, I'm Posting the circuit again... The circuit works well on no load but moment i connect the load one PNP mosfet gets hot and trips the supply. Is there something wrong with the configuration?

 

Repeating the description of your problem is not going to help.

I would open doc any day. Use pdf.

 

Repeating the description of your problem is not going to help.

I would open doc any day. Use pdf.

I too changed it to pnp, but the circuits not working still. what do you mean when you say top mosfet has no dc path for gate? which software are you using for simulation...

Sir,

I'm posting this circuit again. I/p is 5V pwm output, square wave at 100khz, 24 V is applied to mosfets.

Repeating the description of your problem is not going to help.

I would open doc any day. Use pdf.

Sir, What will??

I too changed it to pnp, but the circuits not working still. what do you mean when you say top mosfet has no dc path for gate? which software are you using for simulation...

Input voltage is 5V, square wave pwm, 100khz, mosfets have 24V

 

In your circuit, if D3 is a 15V zener then the voltage at Q6 gate is always 15V above Q3 emitter, i.e never rises above about 19V. That means Q6 is permanently on (unless its Vgs turn-on threshold is unusually high).

 

In your circuit, if D3 is a 15V zener then the voltage at Q6 gate is always 15V above Q3 emitter, i.e never rises above about 19V. That means Q6 is permanently on (unless its Vgs turn-on threshold is unusually high).

Thank you so much for your reply....Should I change the zener to 18V

 

Thank you so much for your reply....Should I change the zener to 18V

Or should I eliminate it completely

 

Q3 emitter voltage can only change by about 4V. Re-consider how you will use that to switch Q6 on and off reliably and whether a more conventional gate driving arrangement would be better.

 

My H-bridge circuit properly uses complementary NPN/PNP 2N3904/2N3906 emitter followers to drive the Mosfets:

 

Q3 emitter voltage can only change by about 4V. Re-consider how you will use that to switch Q6 on and off reliably and whether a more conventional gate driving arrangement would be better.

Sir,
what conventional gate driving arrangement are you suggesting?

 

I would suggest using dedicated off-the-shelf FET bridge driver ICs, such as the IR2110 or its brothers, particularly if you want to switch FETs at high frequency. A problem with your present circuit is that at 100kHz it likely won't be able to handle enough current (~1A or so) to charge/discharge the FET gate capacitances sufficiently fast to prevent over-heating. Your circuit also provides no dead-time to prevent shoot-through by ensuring that the top and bottom FETs never conduct simultaneously during their finite switch-over times.