Problem: I'm using a "zener diode voltage reference" to put 16 V across the HI/LO pins of an optocoupler/MOSFET driver. The configuration constantly draws current, thereby dissipating a lot of power (~watts).

Question: Can I use a MOSFET switch to "turn on" the Zener voltage reference in a window around when I need it, and have it off most of the time?

Details: My application is a negative high-voltage pulse generator (see attached circuit). The output will be connected to a wire (and probe), and nothing else.

Pulse specs:
period = 50 ms
duty cycle = 0.2%

This pulser uses an N-channel Enhancement Mode MOSFET (1500 V, STFW3N150) with the drain connected to a load resistor plus ground, and the source connected to a negative high-voltage supply.

The MOSFET is driven by a FOD3120 optocoupler, whose output floats on the negative high-V rail. For this optocoupler to work, the HI/LO difference must be >12 V. Here I've set it to 16 V.

Originally, I set HI to 16 V above the negative rail with a "Zener voltage reference/divider". The resistor in series with the Zener diode is set to draw enough current (~5 mA) to operate the Zener diode, and have it's voltage drop be 16 V. The Zener diode is bypassed with some caps.

The power dissipation will be an issue in the Zener's resistor. Say the negative rail is at -1000 V. With a current through the Zener of 5 mA, the power will be P = I*V = 5 W!

Important Note: I'm testing this circuit now with lower voltages (~-100 V). Ultimately I'll want to use higher voltages (~-1000 V), and thus some resistors will change. For example, 30k resistor will be more like a 100k resistor.

Solution: Use a P-Channel Enhancement Mode MOSFET (100 V, ZVP2110A) to switch the current through the Zener diode from low to high in a window around the main MOSFET trigger.

Should this work? I've tried wiring it up, but so far it acts as if the P-channel MOSFET isn't even there! Turning the trigger to it on or off doesn't affect the output.... (or the current being drawn, and hence the power).

 

It acts like your Pmos isn't there because it is always turned on, so in effect it isn't there. Pmos is off with a positive voltage on the gate and on with a 0V or negative voltage. You gate square wave is going between 0V and -5V, so always on.

The number one thing for you to do is to drop your voltages to way below the 100V your testing with now, until you learn more about what your doing. Not saying this to put you down, just to keep you alive/save your life. Use around 10V or 12V until you know what your doing, PLEASE!

And might be wrong, but the whole schematic makes no sense. What is the end result you hope to achieve? The purpose of the circuit?

 

Since your input and output share the same ground, what's the purpose of the opt coupler?

 

It acts like your Pmos isn't there because it is always turned on, so in effect it isn't there. Pmos is off with a positive voltage on the gate and on with a 0V or negative voltage. You gate square wave is going between 0V and -5V, so always on.

Oops! I designed this thinking that I needed the gate-source voltage to go negative to turn it on. I had the "shape" of the pulse right in my head, just not the levels! Okay, that's an easy fix.

The number one thing for you to do is to drop your voltages to way below the 100V your testing with now, until you learn more about what your doing. Not saying this to put you down, just to keep you alive/save your life. Use around 10V or 12V until you know what your doing, PLEASE!

No offense taken. This is hard-wired on perf board, not breadboard or anything, and I'm turning everything off between modifications. But I'll be careful.

And might be wrong, but the whole schematic makes no sense. What is the end result you hope to achieve? The purpose of the circuit?

The purpose is to switch the voltage (with respect to ground) on an electrode in an ultra-high vacuum chamber for the purpose of ionizing a collection of suspended, trapped, ultracold atoms.

Everything minus the red part of the schematic is tested and works fine. The optocoupler is necessary to trigger the NMOS, whose source sits at -1000V (under normal operation). The optocoupler only puts out a pulse if the HI is 12V above the LO. This could be done with a battery, or a floating galvanically-isolated power supply, but I've chosen to do it with a Zener diode reference (16V) so that I only need a single high-voltage power supply.

(In case it's not clear - I want a pulse that goes from 0 V to -1000 V really fast (10s of nanoseconds), sits there for a bit, and then goes back to 0 V.)

 

Since your input and output share the same ground, what's the purpose of the opt coupler?

The gate of the N-type MOSFET needs to go +5 V above the MOSFET source to turn on. The source sits at -1000 V, so the gate needs to see:

"off" = -1000 V
"on" = -997 V or higher

The input trigger pulse is coming from a BNC 565 Pulse Delay Generator which is ground referenced. The optocoupler turns a 0V-to-5V pulse to a (-1000V)-to-(-984V) pulse.

 

Why negative volts? Having a positive on one electrode and switching the 0V/common electrode off and on would do the same thing. But without all safety precautions being followed both ways are dangerous. Negative volts will kill the same as positive.

 

Why negative volts? Having a positive on one electrode and switching the 0V/common electrode off and on would do the same thing. But without all safety precautions being followed both ways are dangerous. Negative volts will kill the same as positive.

After ionization, we detect the free electrons. Ionization is caused by the sudden presence of a high electric field, which also "shoots" or directs the electrons towards/away from the detector (depending, as you point out, on the direction of the electric field).

Having a high electric field next to the detector has been shown to mess up the detector's performance, especially for a spatial phosphor detector we have placed behind the microchannel plate detectors. So we prefer to "shoot" the electrons towards the detector from the other side, and this requires a "negative" pulse on the electrode positioned opposite to the detector.

(Usually we do this with a trigger transformer circuit that produces pulses in the kV, so I'm no stranger to safety around high voltage. But I appreciate your concern. Certainly, one should keep things low when testing a circuit.)

 

Looking at your schematic again and rereading the thread there are more problems. your Nmos is wired backward, the intrinsic diode in it is conducting even when gate is off.

You said your putting 5V on the gate that is the thresh hold voltage, Vgs(th). This is really the shut off voltage of a mosfet. You want Vgs voltage on the gate, this will turn it fully on. Using Vgs(th) makes a mosfet abig resistor that will soon burn out.

I'm trying to help you but I can see this thread having a short lifespan due to the high voltage and inexperience/mistakes.

 

Looking at your schematic again and rereading the thread there are more problems. your Nmos is wired backward, the intrinsic diode in it is conducting even when gate is off.

I don't see this. For an N-channel enhancement mode MOSFET, the load needs to be on the drain side, and most circuits I have seen (e.g. Horowitz & Hill) put the drain at a positive voltage with respect to the source. That is how I have mine wired: load resistor (3k) on drain side, drain = 0 V, source = -100 V, so drain is 100 V above source, and current flows from drain to source.

Also, I'm positive that for a N-channel enhancement mode MOSFET, the gate must go positive with respect to the source for it to go from non-conducting to conducting, which is how I have it wired.

You said your putting 5V on the gate that is the thresh hold voltage, Vgs(th). This is really the shut off voltage of a mosfet. You want Vgs voltage on the gate, this will turn it fully on. Using Vgs(th) makes a mosfet abig resistor that will soon burn out.

I agree that 5 V is near the threshold voltage (typically 4 V according to the spec sheet). To make sure it is fully conducting ("on"), the gate voltage is set to go 16 V above the source in the drawing I provided. (The FOD3120 outputs a 16 V pulse when the HI/LO voltage is set to 16 V. The 16 V Zener diode does this.)

I'm trying to help you but I can see this thread having a short lifespan due to the high voltage and inexperience/mistakes.

I apologize sincerely for my inexperience and my mistakes. But I can't stress enough that this circuit sits on a table several feet from me when the power supplies are on, and all power supplies are shut off whenever I even approach the circuit. Also as a precaution, I do not work alone.

 

And the intrinsic diode conducts from source to drain. Mosfets also are bipolar devices, they will conduct both directions with gate on. If you have a power supply that can give you the necessary negative voltage, you can still use your Nmos as a low side switch. Put your negV on one electrode and wire the othher electrode to the Nmos and common. The Negative voltage would be active all the time but when the mosfet conducts it will complete the circuit. And give your spark. And the gate will only need your 16V.

 

I don't see any major problems with your circuit, EXCEPT:
1. The PMOS is subjected to the negative supply voltage.
2. The PMOS you chose requires -10V to guarantee Rds(on). -5V is iffy.
3. Most resistors have a voltage limit of 250-500V. You might need several in series when you get to 1kV. See the individual resistor's datasheet.
Your duty cycle is so low, you could use a 10Meg resistor for the zener with 1kV. You would only get about 100uA average current, but the zener voltage should still exceed 15V. You could also get by with less than 4uF across the zener, because the gate capacitance of your NMOS is only about 1nF. Maybe you wouldn't need to switch the zener bias current.

I don't know why your PMOS appeared to always be ON. If you were only looking at the zener voltage, the 4uF in parallel would hold the voltage for the 100+ us that the current is switched off.

 

And the intrinsic diode conducts from source to drain. Mosfets also are bipolar devices, they will conduct both directions with gate on. If you have a power supply that can give you the necessary negative voltage, you can still use your Nmos as a low side switch. Put your negV on one electrode and wire the othher electrode to the Nmos and common. The Negative voltage would be active all the time but when the mosfet conducts it will complete the circuit. And give your spark. And the gate will only need your 16V.

I'm not sure I follow that 100% (by electrode do you mean the electrodes I mentioned that are in the vacuum chamber, or are you referring to the drain/source of the Nmos?).

BUT, I'll admit that I hadn't thought seriously before about operating the Nmos as a low side switch. I dismissed it because I thought it wouldn't turn on, but now I think I see how it's done - float the gate on the source, and don't ground reference it (as I had had it in my mind when thinking about low side Nmos configurations).

So I've drawn up what's in my head and what I think you might be suggesting. (attached)

At first I thought it wouldn't work again, because I thought that when the MOSFET conducts, the gate would suddenly be WAY more positive than the source - but now I see that as the source gets shorted with the drain, it drags the gate down to +15V above the drain potential, too. So all's well! V_GS remains +15V and the MOSFET doesn't immediately shut off. Assuming I'm understanding correctly.

Also, thanks for your helpful comments.

I don't see any major problems with your circuit, EXCEPT:
1. The PMOS is subjected to the negative supply voltage.
2. The PMOS you chose requires -10V to guarantee Rds(on). -5V is iffy.
3. Most resistors have a voltage limit of 250-500V. You might need several in series when you get to 1kV. See the individual resistor's datasheet.
Your duty cycle is so low, you could use a 10Meg resistor for the zener with 1kV. You would only get about 100uA average current, but the zener voltage should still exceed 15V. You could also get by with less than 4uF across the zener, because the gate capacitance of your NMOS is only about 1nF. Maybe you wouldn't need to switch the zener bias current.

I don't know why your PMOS appeared to always be ON. If you were only looking at the zener voltage, the 4uF in parallel would hold the voltage for the 100+ us that the current is switched off.

Thanks for taking a look at it. I didn't actually know that basic 1/4W resistors sometimes/often have voltage ratings (btw, I was planning on using 1 W resistors to be safe); I just thought they had power ratings. So yes, if I go ahead with this and scale it up, I'll check the ratings and probably string 3-4 of them together in series.

The BNC 565 can put out at least 12 V pulses, so I should be good there, but in testing the lower-V version, I was using 5 V pulses on the Pmos, so I'll try upping the amplitude (in addition to shifting the whole thing up to be an inverted, positive going pulse). (Also, just realized I lied earlier - I plan on using the BNC 565 in the final implementation, but for testing I'm using an Agilent 33220 20 MHz Function Generator.)

Also, I'll take a look at my Zener diode. Maybe I can get away with a lower current to get the necessary reverse voltage drop. In which case the whole switching thing might not be necessary. (It also might not be necessary if the low side switch - attached - would work.) Thanks for the observation.

 

I don't get it. your original circuit is using the NMOS as a low side switch.
Your new circuit has -20V on the drain. What's that supposed to do? The drain always has to be positive with respect to the source. Otherwise, the substrate diode will conduct.

 

I don't get it. your original circuit is using the NMOS as a low side switch.
Your new circuit has -20V on the drain. What's that supposed to do?

Oops, terminology-wise I was thinking "low side switch" meant the load was on the source-side. But now that reasoning doesn't make much sense, and thankfully there exists a thread that has some info:

http://forum.allaboutcircuits.com/showthread.php?t=51680

The drain always has to be positive with respect to the source. Otherwise, the substrate diode will conduct.

Oh right. Yes of course. But this would work if the drain was more positive than the source, right? (I got carried away thinking anew about MOSFETs as bipolar devices re: shortbus's comments, and forgot about the substrate diode.)

 

I finished testing the circuit at low-voltage. Two notes:

1. The control pulse for the p-channel MOSFET did need to go negative with respect to ground. I'd be interested to hear if this contradicts what others think should be correct, because it definitely works with a 0/-10 V pulse, and does not work with a 0/+10 V pulse. Remember, the source is at ground (0 V) in this configuration.
2. The huge capacitance across the Zener diode made HI take a really long time to reach 16V above the negative rail. Replacing the four 1uF caps with a single 0.1uF cap reduced the decay time (90% to 10%) to about 1.5 ms, which is acceptable.

I calculated the appropriate resistors for the drain's of the p- and n-channel MOSFETs. In the p-channel case, I wanted 5 mA at 500 V, but wanted to keep the power to well within the resistors' specs. A total resistance of 120K seemed to be a nice fit, spread across 4 1/2 Watt 1% metal oxide resistors.

I've attached scope traces of the control pulse timing (blue = p-channel, pink = optocoupler, yellow = output), the entire output pulse (at -500 V), and just the leading edge.

Some additional notes:

• The p-channel is ON for about 1.5 ms. At a rep rate of 20 Hz, this reduces the power consumption due to the Zener diode voltage reference by 97%.
• The risetime looks to be around 40 ns, which is fine.
• There's a fair bit of overshoot. The "top" of the pulse isn't all that flat, and decays a bit.
• The Zener diode turns on at a reverse bias current of 2.7 mA, which works out to be about 350 V, which is what I see in my tests.
• The circuit works fine at least up to -1000 V, BUT begins to overheat near -1000 V. There are not overheating issues (no fan) at the intended application voltage (-500 V).

Thanks again for everyone's help.

 

I finished testing the circuit at low-voltage. Two notes:

1. The control pulse for the p-channel MOSFET did need to go negative with respect to ground. I'd be interested to hear if this contradicts what others think should be correct, because it definitely works with a 0/-10 V pulse, and does not work with a 0/+10 V pulse. Remember, the source is at ground (0 V) in this configuration.

1. Just as predicted (by me, anyway).
   

   [*]The huge capacitance across the Zener diode made HI take a really long time to reach 16V above the negative rail. Replacing the four 1uF caps with a single 0.1uF cap reduced the decay time (90% to 10%) to about 1.5 ms, which is acceptable.

I calculated the appropriate resistors for the drain's of the p- and n-channel MOSFETs. In the p-channel case, I wanted 5 mA at 500 V, but wanted to keep the power to well within the resistors' specs. A total resistance of 120K seemed to be a nice fit, spread across 4 1/2 Watt 1% metal oxide resistors.

I've attached scope traces of the control pulse timing (blue = p-channel, pink = optocoupler, yellow = output), the entire output pulse (at -500 V), and just the leading edge.

Some additional notes:

• The p-channel is ON for about 1.5 ms. At a rep rate of 20 Hz, this reduces the power consumption due to the Zener diode voltage reference by 97%.
• The risetime looks to be around 100 ns, which is fine.
• There's a fair bit of overshoot. The "top" of the pulse isn't all that flat, and decays a bit.
• The Zener diode turns on at a reverse bias current of 2.7 mA, which works out to be about 350 V, which is what I see in my tests.
• The circuit works fine at least up to -1000 V, BUT begins to overheat near -1000 V. There are not overheating issues (no fan) at the intended application voltage (-500 V).

Thanks again for everyone's help.

Where did you find a p-channel MOSFET with >500V breakdown?

 

Where did you find a p-channel MOSFET with >500V breakdown?

In the drawer labeled "MOSFETS" in the lab.

But seriously, I can pretty much guarantee a Digikey search similar to this was the source.

 

In the drawer labeled "MOSFETS" in the lab.

But seriously, I can pretty much guarantee a Digikey search similar to this was the source.

Now I remember. I was searching for a 1kV PMOS.

 

Now I remember. I was searching for a 1kV PMOS.

(Let me know if you find one.)

Is there a clever way to get around the breakdown voltage (say, using multiple FETs, or some other part)? A quick sketch in my notebook suggests to me that there isn't.

 

(Let me know if you find one.)

Is there a clever way to get around the breakdown voltage (say, using multiple FETs, or some other part)? A quick sketch in my notebook suggests to me that there isn't.

Check this out. The simulation limits the voltage across each transistor to about 330V. This is called a cascode configuration.