I am trying to diagnose what is happening in the below circuit I replicated. I successfully used the 40106 inverter to pwm a 12v motor through 1 irfz34n MOSFET. Trying to take that into the h-bridge circuit hasnt worked out. I keep getting direct shorts with no response when I alternate X inputs from 12v to 0v. I have shunted the pwm output signal via a 100ohm resistor from 40106 to h-bridge circuit pwm in. No transistor stage. My component values I chose are:
R=100ohms
Diodes=1n4007
Motor is 12v 2A
N-channel MOSFETs=irfz34n
P-channel MOSFET=irf9530.
All ICs and motor powered by 12v lead acid 9Ah

The calculations on MOSFET charge time and low dump to ground through pwm diode is where I think might be a problem. As I understand the circuit, with X held high, its not the pwm signal that charges the MOSFET gate directly due to diode, but dumps gate charge through diode and is recharged via pull up re sistor. Are these values creating a short or shoot through effect somewhere? Thanks again.

 

I have shunted the pwm output signal via a 100ohm resistor from 40106 to h-bridge circuit pwm in. No transistor stage.

That is likely the cause of your problem. A CD40106 can source/sink only a few mA while providing a decent voltage swing, so needs a buffer stage to drive power MOSFETs at typical PWM frequencies. If there is not enough current to charge/discharge the MOSFET gate capacitances quickly then there will be high shoot-through currents in the MOSFETs.

 

That is true and thanks for pointing that out, however correct me if I am wrong, but in this h-bridge circuit, there is a diode directly in front of the MOSFET gate from the pwm. Would that not prevent voltage/current from charging to begin with? Its only the high low signal itself that controls the gate via pull up resistors and dumps gate through diodes. I am no expert, so I could be very wrong. Please inform me if I am.

 

The diodes provide an OR function and discharge paths for the N-FETs. The resistors are the charging paths for the N-FETs and the discharge paths for the P-FETs. Either the resistors, or the internal resistances of the 40106, limit the current.

 

Consider the case :
X1 is at 12V.
When PWM driven by 40106 goes to 0, it has to sink the current thro' R1, which is 12V/100 Ohms = 120mA (leave the diodes) in addition to discharging gate capacitance charge. 40106 cannot sink so much, (to quote datasheet figures, Vdd=15V, Vo < 1.5V while sinking 3.4mA at 25 deg C). So PWM signal is likely to remain way higher closer to the rails!
I will go with Alec_t reco of buffer.

 

I did not put in an update since I posted, but your diagnosis was spot on. I realized this and changed the resistors to 10k as an experiment. I was concerned about mosfet gate drive time so I wanted a higher current. It was too much. That fixed the pwm signal and the over heating was due to a short that I overlooked. Runs well now. Thank you

 

Good to hear it's sorted.

 

Good to hear it's sorted.

Thank you for the knowledge Alec_t

 

I am trying to diagnose what is happening in the below circuit I replicated. I successfully used the 40106 inverter to pwm a 12v motor through 1 irfz34n MOSFET. Trying to take that into the h-bridge circuit hasnt worked out. I keep getting direct shorts with no response when I alternate X inputs from 12v to 0v. I have shunted the pwm output signal via a 100ohm resistor from 40106 to h-bridge circuit pwm in. No transistor stage. My component values I chose are:
R=100ohms
Diodes=1n4007
Motor is 12v 2A
N-channel MOSFETs=irfz34n
P-channel MOSFET=irf9530.
All ICs and motor powered by 12v lead acid 9Ah

The calculations on MOSFET charge time and low dump to ground through pwm diode is where I think might be a problem. As I understand the circuit, with X held high, its not the pwm signal that charges the MOSFET gate directly due to diode, but dumps gate charge through diode and is recharged via pull up re sistor. Are these values creating a short or shoot through effect somewhere? Thanks again.View attachment 127474 View attachment 127472

PWM in a bridge circuit usually involves increasing the dead time.

Most driver chips include some anyway so the high side and low side conduction periods don't overlap and briefly short the supply.

The complementary outputs are usually driven by a flip-flop. There's a bit of combinatorial logic in front of that - the error amplifiers provide an inhibit pulse that widens the dead time to reduce the mark space ratio.