I'm designing a BLDC Driver.
so I'm Pulse Width Modulating High side MOSFETS and commutating low side MOSFETs and this is the waveform of the gates.
red is Low side GateSource Voltage/ Yellow is High Side GateSource Voltage
I think this happens because of parasitic Gate Drain Capacitance.
and when I add a 50 nF capacitor Between the gate and source the problem goes away(gate resistor is 22 Ohms)(but rise time and fall time increases)! why is this happening? how can I fix this?
so I'm Pulse Width Modulating High side MOSFETS and commutating low side MOSFETs and this is the waveform of the gates.
red is Low side GateSource Voltage/ Yellow is High Side GateSource Voltage
I think this happens because of parasitic Gate Drain Capacitance.
and when I add a 50 nF capacitor Between the gate and source the problem goes away(gate resistor is 22 Ohms)(but rise time and fall time increases)! why is this happening? how can I fix this?
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