Here is the revised sim circuit with SW3 swapped around so that the 30V+ is going to the Source.

I'm not sure why there is a current in the inductor at the start since SW1 is open but it must be due to C1 charging. Then there is the second spike when SW1 closes, and the charge redistributes through the coil. Also, the voltage across C1 is the same as C2 and gradually climbs rather than a higher initial voltage across C1 dropping as it equalises with C2.

The initial spike may be due to stray capacitances (from M2 and other sources) contributing to the initial charging of C1. I will try swapping SW1 for a voltage-controlled switch and see if that removes it.

 

So here is the revised circuit with a voltage-controlled switch in place of the NMOS for SW1. This makes all the difference.
The surprising value is the voltage across C2 when SW1 turns off again

 

Sure, you will obtain unique results, because L1 will instantly lost its energy on every break of SW2.

(Now SW2 is SW1).

The surprising value is the voltage across C2 when SW1 turns off again

So, you have unique results: "million" volts and burned whole setup.

 

(Now SW2 is SW1).

So, you have unique results: "million" volts and burned whole setup.

For my purposes that is all fine. Just needs a ‘calming’ resistor.

 

Please post the .asc file for #54, #57, or #61.

ak

 

Please post the .asc file for #54, #57, or #61.

ak

Here are two.

 

#61

• never use not user named node names at spice plot --or-- IF - then verify they are correct (refering to the node you think they are) at each run !!!
• majority of mosfets have a reverse spike protection diode built in = if you want to use 'em with inductive resonant circuit where voltages the mosfet sees may appear at both polarity for it's quiescent source voltage level you want to use the pairs of them - so both of the protective diodes are never FW biased . . . also the reverse gate to source voltage must be specified higher that the mosfet sees . . .
  • . . . the 30V "excitation" source requires the reverse voltage to be i assume at least 2-ce of that --or-- then you must build in a protective circuitry or design elements that supress the potentially harming voltage excursions
  • . . . another option is to use lesser excitation voltage
• other -- many inductors perform at their best inside of a certain decade range of BW --e.g.-- if it's not a certain circuit you want to tune the operation for -- then i don't see the point of building an expensive test rig for ??

● ??? ferrite beads and diodes with near/below unity resistors may be an option to damp switching artefacts . . . but i guess the nature of your circuit rather benefits from such ocurring rather than supressed ? just use a floating supply per mosfet switch

●● at #62 the extreme spike is likely due the ideal nature of the VC SW and won't be present at real world circuit ←← a workaround for might be to present a 20 to 200 mV negative hysterresis that renders the resistance transition of the switch to be more mild

●●● at real world the 50mH inductor has also a near unity or 10x resistance depending on wire diameter (will suppress oscillations at the closuring of the switches respectively)

 

Thank you for your detailed suggestions. At the moment, I'm exploring simulations and not building anything tangible.

I'm not too worried about the modest spikes that can be handled, but I am curious about the voltages on C1 and C2. If you look at the configuration below, I have flipped M2 around so that its Drain is facing C1, where the charge will be coming from, and when M1 starts conducting, both C1 and C2 charge up, although in principle there should be nothing happening with C2 since M2 is open. This may be explained by stray capacitance, some from M2, charging C2 and where the small current through the inductor at the start reflects that. Then, when M2 closes, we see the main charge transfer and the LC oscillation in L1 and smaller ones in C1 and C2. Also of interest is that we don't see both capacitors settling at around 15V as one might expect, but both at around 0V.




However, if I reverse the orientation of M2, with Source to C1 and the opposite of how I would expect to connect it, then I get this:



Any thoughts on these observations?

 

In the bottom sim (with reversed M2), is V(C2) measured across C2, or from the top of C2 to GND? My guess is that it is from the top of C2 to GND.

I am curious about the voltages on C1 and C2.
...
and when M1 starts conducting, both C1 and C2 charge up,

Nope. C1 charges up, and C2 just follows along. With M2 open and C2 initially completely discharged, there is 0 V across C2 so both ends of it are at the potential of whatever the top of C2 is connected to, which is C1. So the voltage from the top of C2 to GND is exactly the voltage across C1. C2 cannot charge up because M2 is open; there is no current path.

Also, note that while the I(L1) waveform of the second cycle is close to that of the first, it is not identical. This is because there is charge in C2, and a voltage across it, left over from the first cycle. When M2 closes, the step voltage across L1 is lower. If you add a plot that is (V(C2)top - V(C2)bottom), it should show that the true voltage across C2 is not the same after the first cycle.

ak

 

In the bottom sim (with reversed M2), is V(C2) measured across C2, or from the top of C2 to GND? My guess is that it is from the top of C2 to GND.



Nope. C1 charges up, and C2 just follows along. With M2 open and C2 initially completely discharged, there is 0 V across C2 so both ends of it are at the potential of whatever the top of C2 is connected to, which is C1. So the voltage from the top of C2 to GND is exactly the voltage across C1. C2 cannot charge up because M2 is open; there is no current path.

Also, note that while the I(L1) waveform of the second cycle is close to that of the first, it is not identical. This is because there is charge in C2, and a voltage across it, left over from the first cycle. When M2 closes, the step voltage across L1 is lower. If you add a plot that is (V(C2)top - V(C2)bottom), it should show that the true voltage across C2 is not the same after the first cycle.

ak

I haven’t quite assimilated all you have written yet but the C2 plot is N008 (I think) and I assume is referenced to Gnd. Should I instead plot the voltage across both capacitors instead of the two nodal values? And should I switch back M2 so the Drain is connected to C1?

 

the C2 plot is N008 (I think)

To reduce confusion, add a short stub wire to each voltage measurement point and add a net name to the end of the stub. LTS will use the net names instead of node numbers in plots.

And should I switch back M2 so the Drain is connected to C1?

No. Going back to post #13 (and others), the n-channel M2 source goes to GND, and the drain goes to DUT C2. For a more clear idea of how M2 is functioning and which way currents are going, imagine replacing it with an NPN transistor.

ak

 

Here is the differential voltage across C2 and with the M2 Source connected to C1. Looking more reasonable and M2 now hopefully the correct way around.

 

You were asked to label all the nodes of interest so we know which voltage nodes are being plotted.
Why did you not?

You may know where node n005 is but we don't.

Just go the the Edit drop-down menu and select Label Net.

 

Here you are. It's a little different to access on a Mac.

 

if you use a wide supply range high input impedance high-speed op amp - such as https://www.physics.wisc.edu/courses/home/spring2023/623/ds/LF357-opamp.pdf // https://www.analog.com/media/en/technical-documentation/data-sheets/lt0155.pdf -- then you are likely able to measure all voltage points of your circuit - avoiding fancy circuitry
. . . but it's still likely more safe if you drop your test circuit voltage to below 18V @ ▼