I want to devise an IC-based control for a simple circuit that equalises the voltage across two capacitors, so I can observe the behaviour of the inductor.

The sequence of events is this: SW1 is closed for a short while to charge up C1. SW1 is opened, and then SW2 is closed, so charge flows to C2 and the voltages equalise. This is the layout:



To be able to play around with the timings, I am devising a system where, as soon as SW1 is opened, by the falling edge of the external signal driving the MOSFET for the switch, there is then an adjustable delay before SW2 is closed. Once SW2 is closed, it remains so for an adjustable period (e.g. 0.1s) before opening, and the cycle repeats with SW1 closing when the external signal goes high for say 5% duty at 1Hz.

I asked AI to come up with a circuit based on a dual monostable that would do this, and it has produced what is in the next diagram, which is pretty rubbish, actually. So almost starting from scratch, I need to use a dual monostable to achieve the following sequence:



With reference to the first diagram, an external signal generator, operating at 1Hz and with a duty of 5% (i.e. an on time of 50ms) switches on SW1, comprising a driver and a MOSFET.

C1 charges up to the battery voltage and then, after SW1 reopens when the external signal goes low, I need an adjustable delay before SW2 (same driver and FET) closes for an adjustable period to allow the charge equalisation. The adjustable delay can be between 0.1 and 1.0s, and SW2 can be closed for between 0.05 and 0.5s.

Then the cycle starts again with the external signal closing SW1 again etc.

Any clarification and suggestions would be appreciated.

Thanks

 

I want to devise an IC-based control for a simple circuit that equalises the voltage across two capacitors, so I can observe the behaviour of the inductor.

Behaviour of the inductor:
https://forum.allaboutcircuits.com/...-the-inductance-of-a-coil.203763/post-1948304

 

The #1 "schematic" has three critical errors:

1. There is no connection between either the clock source or the A monostable outputs and the B monostable trigger inputs.

2. The two complimentary A outputs are shorted together.

3. Nothing is driving the gate of SW1.

(1) - I understand that this is not your schematic, but this indicates a systemic problem with schematics that do not use industry standard symbols and conventions. If the two monostable halves were shown as separate decals, like the individual inverter that is 1/6 of a hex inverter package, it would be clear that there is no connection between the two. A schematic is a signal diagram, not a wiring diagram and not an assembly drawing. It tells the story and conveys the intent of the designer. Develop the habit now and it will protect you down the road.

ak

One thing the AI got right: GND symbols a.l.w.a.y.s. point down.

 

Oh well, there's hope for AI yet then.

I accept that it got its knickers in a twist, so I am having to start again. The SW1 source is a CMOS signal from an external signal generator.

I intend to achieve the signal sequence described at the end of the original post. I believe a single dual monostable can do it, so is my intention justified?

It would probably be most helpful to the cause if I attempted to draw up my own schematic and then I post that and people can comment and suggest corrections. I will do that on Thursday.