I want to devise an IC-based control for a simple circuit that equalises the voltage across two capacitors, so I can observe the behaviour of the inductor.

The sequence of events is this: SW1 is closed for a short while to charge up C1. SW1 is opened, and then SW2 is closed, so charge flows to C2 and the voltages equalise. This is the layout:



To be able to play around with the timings, I am devising a system where, as soon as SW1 is opened, by the falling edge of the external signal driving the MOSFET for the switch, there is then an adjustable delay before SW2 is closed. Once SW2 is closed, it remains so for an adjustable period (e.g. 0.1s) before opening, and the cycle repeats with SW1 closing when the external signal goes high for say 5% duty at 1Hz.

I asked AI to come up with a circuit based on a dual monostable that would do this, and it has produced what is in the next diagram, which is pretty rubbish, actually. So almost starting from scratch, I need to use a dual monostable to achieve the following sequence:



With reference to the first diagram, an external signal generator, operating at 1Hz and with a duty of 5% (i.e. an on time of 50ms) switches on SW1, comprising a driver and a MOSFET.

C1 charges up to the battery voltage and then, after SW1 reopens when the external signal goes low, I need an adjustable delay before SW2 (same driver and FET) closes for an adjustable period to allow the charge equalisation. The adjustable delay can be between 0.1 and 1.0s, and SW2 can be closed for between 0.05 and 0.5s.

Then the cycle starts again with the external signal closing SW1 again etc.

Any clarification and suggestions would be appreciated.

Thanks

 

I want to devise an IC-based control for a simple circuit that equalises the voltage across two capacitors, so I can observe the behaviour of the inductor.

Behaviour of the inductor:
https://forum.allaboutcircuits.com/...-the-inductance-of-a-coil.203763/post-1948304

 

The #1 "schematic" has three critical errors:

1. There is no connection between either the clock source or the A monostable outputs and the B monostable trigger inputs.

2. The two complimentary A outputs are shorted together.

3. Nothing is driving the gate of SW1.

(1) - I understand that this is not your schematic, but this indicates a systemic problem with schematics that do not use industry standard symbols and conventions. If the two monostable halves were shown as separate decals, like the individual inverter that is 1/6 of a hex inverter package, it would be clear that there is no connection between the two. A schematic is a signal diagram, not a wiring diagram and not an assembly drawing. It tells a story, and conveys the intent of the designer. Develop the habit now and it will protect you down the road.

ak

One thing the AI got right: GND symbols a.l.w.a.y.s. point down.

 

Oh well, there's hope for AI yet then.

I accept that it got its knickers in a twist, so I am having to start again. The SW1 source is a CMOS signal from an external signal generator.

I intend to achieve the signal sequence described at the end of the original post. I believe a single dual monostable can do it, so is my intention justified?

It would probably be most helpful to the cause if I attempted to draw up my own schematic and then I post that and people can comment and suggest corrections. I will do that on Thursday.

 

It would probably be most helpful to the cause if I attempted to draw up my own schematic and then I post that and people can comment and suggest corrections.

Always the best path.

Based on what we know, there is a good chance that not all of your timer circuits need to be a complete monostable. There are other timing circuits that need fewer parts, and these might work for some of your stages because the individual timing windows do not overlap. You have three timers in series, and we need . . .

More data:

Range of system clock frequency?

Range of SW1 ON time? Is SW1 driven directly by the input clock signal?

Range of deadband time between SW1 OFF and SW2 ON?

Range of SW2 ON time?

Range of time between SW2 OFF and the next clock edge?

And - have you thought about how you are going to discharge C1 and C2 between cycles? Residual charge in C1 probably is not a problem since it is being topped off each cycle. However, C2 will have a voltage across it after receiving charge through L1. If this is not discharged at the end of a cycle, the peak current through the inductor will decrease with each succeeding cycle. The solution for this is adding a third times in the string. All of this can be done with one CD40106 Schmitt trigger hex inverter.

ak

 

So here is just the redrawn monostable schematic, which is designed to do the following:

The external signal generator, operating at 0.5Hz and with a duty of 10% (so on time 200ms), closes SW1 (not shown). When that opens on the falling edge of this signal, then that starts the delay when the negative edge enters pin 5. After the adjustable delay (e.g. 0.3s), the output from pin 6 enters the negative edge B input pin 11, causing pin 10 to go high, and SW2 closes for a preset duration (e.g. 0.2s), and opens again after that. Then the cycle repeats with SW1 closing when the next external trigger goes high.

I have only included here the monostable components.

Any reason why this won't work? I know the CD4538 is very old, so maybe there is a 'faster and cleaner' switching device available now which can do the same thing?

 

The CD4538 is fine. You still need a way to reset the capacitor that is being switched by SW2.

To discuss how the timing circuits work with the test circuit in post #1, they both have to be in the same schematic (with unique reference designators)

ak

 

Seems it is working

ADDED:

Thanks for that. Is the U1-U6 set the equivalent of the monostable? If so can you upload the sim (asc) file for me to play with as that would be very helpful.

U1 - oscillator
U2-U6 - MOSFET driver
File L-test.asc uploaded.

Except that one end of L1 is grounded, unlike the schematic in post #1 . . .

Oscilloscope is grounded too...

A better reference designator would be U1A, U1B, etc.

You can not randomly use A - F, because they linked to pin numbers, so it may interfere with optimal circuit board tracing.

 

Seems it is working
View attachment 366485

Thanks for that. Is the U1-U6 set the equivalent of the monostable? If so can you upload the sim (asc) file for me to play with as that would be very helpful.

 

Seems it is working

Except that one end of L1 is grounded, unlike the schematic in post #1 . . .

ak

 

Is the U1-U6 set the equivalent of the monostable?

No. U1 is configured as a squarewave oscillator. The mark and space times are individually adjustable with R1 and R2.

U1-U6 are the six sections of a hex inverter. A better reference designator would be U1A, U1B, etc. He has 5 of them in parallel for increased current drive into/out of the MOSFET's gate capacitance, for faster switching action.

ak

 

No. U1 is configured as a squarewave oscillator. The mark and space times are individually adjustable with R1 and R2.

U1-U6 are the six sections of a hex inverter. A better reference designator would be U1A, U1B, etc. He has 5 of them in parallel for increased current drive into/out of the MOSFET's gate capacitance, for faster switching action.

ak

So these configurations should show in the uploaded asc file so I can see how they are set.

My two capacitors are planned to be 100uF each which I assume will just change and lower the oscillation frequency during each ‘ring’ with the 510mH inductor.

I understand the CD14538 is a more modern version but the function should be similarly simulated by the above sim?

 

Here is a first-pass, *concept* schematic that should meet the requirements in post #1 and post #6. At this time the design does not address resetting C2 between cycles.

T1 - Time for one cycle to complete: 0.8 s
T1 - Q1 on time: 0.2 s
T1 - Time for C1 to charge: 0.2 s
T2 - Time delay before Q2 comes on: 0.3 s
T3 - Q2 on time: 0.2 s

The positive half-cycle of the input clock is 200 ms. This is the time Q1 is on and charging up C1.

When the clock goes low, U1A output goes high and C4 begins charging up through R4. The C4 voltage reaches the upper threshold of U1B in time T2. At that time, U1B out goes low, pulling C5 low. This drives the U1C output high, turning on Q2 and connecting C2 to GND during time T3.

D3 and D4 reset timing capacitors C4 and C5 when the input clock goes high.

Note: The component values shown are not recommendations; they are pulls from my design libraries. Click on the schematic for a larger image.

ak

 

Here is a first-pass, *concept* schematic that should meet the requirements in post #1 and post #6. At this time the design does not address resetting C2 between cycles.

T1 - Time for one cycle to complete: 0.8 s
T1 - Q1 on time: 0.2 s
T1 - Time for C1 to charge: 0.2 s
T2 - Time delay before Q2 comes on: 0.3 s
T3 - Q2 on time: 0.2 s

The positive half-cycle of the input clock is 200 ms. This is the time Q1 is on and charging up C1.

When the clock goes low, U1A output goes high and C4 begins charging up through R4. The C4 voltage reaches the upper threshold of U1B in time T2. At that time, U1B out goes low, pulling C5 low. This drives the U1C output high, turning on Q2 and connecting C2 to GND during time T3.

D3 and D4 reset timing capacitors C4 and C5 when the input clock goes high.

Click on the schematic for a larger image.

ak
View attachment 366497

Why are proposing this when the revised design I posted fully does what I need?

 

what is the actual data-/information -target you hope to extract from this experiment ?
? what are the real values for the capacities and the inductor
? what is the input data/parameters you hope to be able to log with suffient accuracy for any post-analysis conclusions

the voltages on capacitors can be monitored by j-Fet op amp - but they are changing relatively fast at low capacities ++ the switching adds a settling time for op amp = a dealy before the valid output appears at op amp (may be several microseconds)

another problem is the large inductor with parasitic properties (self-resonance , inter-winding capacitance , core magnetizing time)
https://www.google.com/search?q=per...tization+at+unipolar+excitation&channel=entpr

 

what is the actual data-/information -target you hope to extract from this experiment ?
? what are the real values for the capacities and the inductor
? what is the input data/parameters you hope to be able to log with suffient accuracy for any post-analysis conclusions

the voltages on capacitors can be monitored by j-Fet op amp - but they are changing relatively fast at low capacities ++ the switching adds a settling time for op amp = a dealy before the valid output appears at op amp (may be several microseconds)

another problem is the large inductor with parasitic properties (self-resonance , inter-winding capacitance , core magnetizing time)
https://www.google.com/search?q=per...tization+at+unipolar+excitation&channel=entpr

As specified earlier 100uF for the caps and suggested 50mH for the primary of transformer. Exploring and logging the voltage transfer (C1 to C2) and the efficiency of energy transfer, and voltage across, the inductor as a function of the SW2 pulse width and SW1 closure frequency. Initially I will just record the open circuit voltage across the inductor but in time may need something like you suggest for data logging. The larger C values will slow down the voltage ramps.

There is also a plan to monitor behaviour when L and C2 are acting as a 1/4 wave resonator.

 

https://www.nexperia.com/product/PSMN1R3-30YL might be an overkill
. . .
? theres nothing much interesting about it ~ unless you won't damp spurious oscillations.

 

As specified earlier 100uF for the caps and suggested 50mH for the primary of transformer. Exploring and logging the voltage transfer (C1 to C2) and the efficiency of energy transfer, and voltage across, the inductor as a function of the SW2 pulse width and SW1 closure frequency. Initially I will just record the open circuit voltage across the inductor but in time may need something like you suggest for data logging. The larger C values will slow down the voltage ramps.

There is also a plan to monitor behaviour when L and C2 are acting as a 1/4 wave resonator.

You can start your research right now:

 

You can start your research right now:
View attachment 366530

That’s handy. I will add it to my list of Sim to dos. Is it worth trying to model the 4538 or instead use the special ‘one shot’ function?

 

That’s handy. I will add it to my list of Sim to dos. Is it worth trying to model the 4538 or instead use the special ‘one shot’ function?

In simulation #18, C1, charged up to 30 V, discharges through series connected L1 and C2.
You can see all information about this process and do not need (I think) to model something else.