To address your first comment in post 32, how do I connect the cap being measured to the op amp, in particular the negative side?
. . .

the question is the susceptibility of loosing stability on "overdrive" of the particular amplifier

https://www.eevblog.com/forum/projects/opamps-die-pictures/msg6126579/#msg6126579

i don't remember using cmos deavices in practice . . . so i'm as clueless as you in this

however the protection clamps may have signifficant capacitance that may provide some low pass ~ but tieing positive (non-inverting) input to ground capacitively - may cause instability

on the other hand - i rarely use CMOS coz thay need strong drive (which may be benefit at your case)
https://ww1.microchip.com/downloads...1U-2-4-1-MHz-Low-Power-Op-Amp-DS20001733L.pdf ←←the Fig.4-2 looks not suitable at non de-coupled connection . . .

. . . in one word ► you must know your Op Amp responce at various situations - to be able to make right decisions ~ on how to set it up for the given "environment" . . . (? a switched inductor ? . . . . . . and then it goes to ADC of MCU ← about sensor responce speed vs sampling rate versus analog input is valid ??? estimation of ←←← all this is a tough nut to crack through !!!)

you must - in advance - test the op amp for the best responce configuration

more :

considering only the potential input over- current/-voltage -- the https://www.ti.com/lit/ds/symlink/opa2206.pdf#page=14 --or-- https://www.analog.com/media/en/tec...ta-sheets/ada4177-1_4177-2_4177-4.pdf#page=17 . . . would be more justified ?

but you have 30V test circuit to be interfaced to 5V sensor one ←← which redefines the entire concept =
= a wild guess :: you have to extract your data with least interference ← suggests a j-Fet ?? driven into fixed voltage step above the input signal level ← that gives you an isolation ~ then translate it to MCU reference space ???

the circuit still sinks current from input up to 72uA at 30v
it sinks about 1uA from 3 to 11V input (optimal range)
it's likely possible to drive the sources of the j-Fets abit above the input voltage (the 1 being measured)

▀ ▼ ▀ is what i aimed -- the output range is limitted by the output range of the Op Amp and the DC offset for fet

 

Here is a first pass concept schematic. It is a re-draw of your #37 schematic. The power section is almost identical to yours, with one approach of how to "fix" the grounds.

The test rig is completely floating with respect to the signal GND for the opamp circuit, which is why it has no ground symbol for its control circuits. I show the timing circuit powered from the test rig battery because this simplifies things. None of your schematics show in complete detail how the timing circuit actually drives the MOSFETs, so I show a common way.

Note that none of the part numbers are recommendations; they are components in my design libraries that are close in the decal and pinout to what you have indicated. In particular, Q2 should be as low-rated as possible. Its gate capacitance will have a direct effect on its turn-off fall time, which will alter the shape of the voltage waveform across CT2.

The circled signal ground connection below CT2 needs some discussion.

Click on the schematic for a larger image.

ak

 

the question is the susceptibility of loosing stability on "overdrive" of the particular amplifier

https://www.eevblog.com/forum/projects/opamps-die-pictures/msg6126579/#msg6126579

i don't remember using cmos deavices in practice . . . so i'm as clueless as you in this

however the protection clamps may have signifficant capacitance that may provide some low pass ~ but tieing positive (non-inverting) input to ground capacitively - may cause instability

on the other hand - i rarely use CMOS coz thay need strong drive (which may be benefit at your case)
https://ww1.microchip.com/downloads...1U-2-4-1-MHz-Low-Power-Op-Amp-DS20001733L.pdf ←←the Fig.4-2 looks not suitable at non de-coupled connection . . .

. . . in one word ► you must know your Op Amp responce at various situations - to be able to make right decisions ~ on how to set it up for the given "environment" . . . (? a switched inductor ? . . . . . . and then it goes to ADC of MCU ← about sensor responce speed vs sampling rate versus analog input is valid ??? estimation of ←←← all this is a tough nut to crack through !!!)

you must - in advance - test the op amp for the best responce configuration

more :

considering only the potential input over- current/-voltage -- the https://www.ti.com/lit/ds/symlink/opa2206.pdf#page=14 --or-- https://www.analog.com/media/en/tec...ta-sheets/ada4177-1_4177-2_4177-4.pdf#page=17 . . . would be more justified ?

but you have 30V test circuit to be interfaced to 5V sensor one ←← which redefines the entire concept =
= a wild guess :: you have to extract your data with least interference ← suggests a j-Fet ?? driven into fixed voltage step above the input signal level ← that gives you an isolation ~ then translate it to MCU reference space ???

the circuit still sinks current from input up to 72uA at 30v
it sinks about 1uA from 3 to 11V input (optimal range)
it's likely possible to drive the sources of the j-Fets abit above the input voltage (the 1 being measured)
View attachment 366642View attachment 366644
▀ ▼ ▀ is what i aimed -- the output range is limitted by the output range of the Op Amp and the DC offset for fet
View attachment 366648

Yes, the j-fet option I have posted in #37. Otherwise a simple scoping should suffice.

 

Here is a first pass concept schematic. It is a re-draw of your #37 schematic. The power section is almost identical to yours, with one approach of how to "fix" the grounds.

The test rig is completely floating with respect to the signal GND for the opamp circuit, which is why it has no ground symbol for its control circuits. I show the timing circuit powered from the test rig battery because this simplifies things. None of your schematics show in complete detail how the timing circuit actually drives the MOSFETs, so I show a common way.

Note that none of the part numbers are recommendations; they are components in my design libraries that are close in the decal and pinout to what you have indicated. In particular, Q2 should be as low-rated as possible. Its gate capacitance will have a direct effect on its turn-off fall time, which will alter the shape of the voltage waveform across CT2.

The circled signal ground connection below CT2 needs some discussion.

Click on the schematic for a larger image.

ak
View attachment 366653

Thanks. The core of my timing circuit is shown in #6. I didn’t want to post the whole circuit as that bleeds the discussion out to other areas.

 

Here is the adjusted logging circuit with the revised Iso Gnd for the op-amp. I am equally interested in the switching transients and ringing in L1 due to the opening and closing of SW1, so just scoping across C7 (C2) and also T1 (L1) will be of value. At least the option is there if I choose to use the ADC for recording and analysis. I don't know how many bits/s I could acquire, but enough I hope to build a good picture.

 

I didn’t want to post the whole circuit as that bleeds the discussion out to other areas.

What areas? Something like this?

 

... first pass concept schematic ...

about https://www.onsemi.com/pdf/datasheet/lmv358-d.pdf like an CMOS device Ti suggests one with improved sensitivity https://www.ti.com/product/TLV9002 ?

(i'm a sort of op amp-s addict - so i gonna make a quick spice eval. ...)

 

about https://www.onsemi.com/pdf/datasheet/lmv358-d.pdf like an CMOS device Ti suggests one with improved sensitivity https://www.ti.com/product/TLV9002 ?

(i'm a sort of op amp-s addict - so i gonna make a quick spice eval. ...)

As you wish

 

Schematic #45 - the blue wire connection:

On my schematic #42, ignore the circled GND symbol, connect the same two points, and see how that looks.

ak

 

about https://www.onsemi.com/pdf/datasheet/lmv358-d.pdf like an CMOS device Ti suggests one with improved sensitivity https://www.ti.com/product/TLV9002 ?

As I said in my post, I am not in any way recommending the LM358 for this application. It was a convenient grab because it had the right pinout.

ak

 

... right pinout.

the problem to address is 30V test circuit ~vs~ 3.3V monitoring circuit
the OP should either "equallize" the voltage levels or scale it down for both - op amp & ADC .... & it's a complex one if there's an intention to use lower name value inductor and/or capacitors . . .

 

the problem to address is 30V test circuit ~vs~ 3.3V monitoring circuit
the OP should either "equallize" the voltage levels or scale it down for both - op amp & ADC .... & it's a complex one if there's an intention to use lower name value inductor and/or capacitors . . .

I will scope the caps and inductor and then use those findings to determine how best to setup an ADC logging system. What I have so far provides a reasonable basis for later.

Thanks for your input.

 

Model of full circuit:

 

Model of full circuit:
View attachment 366743 View attachment 366757

Thanks. I had produced something similar myself.

 

Аnother setup, using 50 mH inductor, two 25 μF capacitors and two switches,
continuously converts 30 V DC to 600 Vp, 101 Hz, AC voltage:

 

There are a couple of issues with the #54 sim. First, M1 is in backwards. The internal body diode points toward the source, so it is forward biased continuously, including when M1 is supposed to be off. If you add a short delay before the initial SW3 pulse, you might see that the current spike is at the start of the simulation rather than at the start of V2.

M2 also is in backwards.

ak

 

There are a couple of issues with the #54 sim. First, M1 is in backwards. The internal body diode points toward the source, so it is forward biased continuously, including when M1 is supposed to be off. If you add a short delay before the initial SW3 pulse, you might see that the current spike is at the start of the simulation rather than at the start of V2.

M2 also is in backwards.

ak

I'm not sure what the problems are. M1 is a PMOS (so its body diode points outwards and away from the depletion zone) with its Drain connected to the + of the 30V supply, the source is connected to the load (C1) and with V2 driving the Gate. How else would a PMOS be operated? Do you mean I should be pulling the voltage down instead of up to operate it, as with a real-world PMOS?

M2 is a NMOS (body diode pointing inwards) connecting the bottom of C1 and C2 and with its Gate driven by V3. If I rotated them both 90 degrees clockwise, they would look like regular FETs.

You will need to explain why these are both wrong in your view.

I see the spike at the beginning rather than later in a cycle, but haven't figured out why that is.

V2 is set to close SW3 for 0.2s at the start of a cycle (so C1 charges up) and then V3 is set to close SW1 for 0.1s after a delay of 0.5s, so that's 0.3s after SW3 opens again. I've put the circuit here again, and in the bottom graph, one can see the correct timing sequence.

 

Аnother setup, using 50 mH inductor, two 25 μF capacitors and two switches,
continuously converts 30 V DC to 600 Vp, 101 Hz, AC voltage:

View attachment 366771

Does this sim circuit do exactly what my original post set out to show, that is the current equalizing between the two capacitors and showing a spike at the inductor when current initially flows in that process? Your sim shows a build up of voltage so is each of the oscillations a spike of sorts?

 

I'm not sure what the problems are.

You have both FET switches configured as source-followers rather than as "saturated" switches.

I have no idea what is and is not in the generic FET model. To adapt your schematic for the real world, add a 1N914 diode across each FET's drain and source, with the orientation the same as on power MOSFET datasheets, and trace the startup battery current with both switches off.

https://www.vishay.com/docs/91020/sihf530s.pdf

https://www.vishay.com/docs/91278/sihfr902.pdf

ak

 

Does this sim circuit do exactly what my original post set out to show, that is the current equalizing between the two capacitors and showing a spike at the inductor when current initially flows in that process? Your sim shows a build up of voltage so is each of the oscillations a spike of sorts?

Capacitors C1 and C2 are connected in parallel through V1 and are connected to point "A" through SW.
Therefore, on AC, C1, C2 and L1 are connected in parallel and represent oscillatory circuit with resonant frequency 101 Hz.
Switch SW toggles point "A" every 4.965ms between poles of V1, so provide 30 V AC to tank, through L1.
Voltage on C1 and C2 is pure sine 600 Vp, without step.