In simulation #18, C1, charged up to 30 V, discharges through series connected L1 and C2.
You can see all information about this process and do not need (I think) to model something else.

Ok, but things might change if resonance is introduced to the series LC circuit, as that will surely change the behaviour of the setup.

 

Ok, but things might change if resonance is introduced to the series LC circuit, as that will surely change the behaviour of the setup.

Resonance:

 

Resonance:
View attachment 366545

How did you set the frequency to the right value or have you swept a wide range. Is the range used 0-101 Hz? I wasn’t sure how the series configuration of caps either side of the inductor would behave but it seems similar to a single series L and C. I must get these sims running on my Mac and play with different values. Thank you for the input.

 

How did you set the frequency to the right value or have you swept a wide range. Is the range used 0-101 Hz?

I found resonance frequency by this way:
(See .AC in LTspice help)

 

what is the actual data-/information -target you hope to extract from this experiment ?
? what are the real values for the capacities and the inductor
? what is the input data/parameters you hope to be able to log with suffient accuracy for any post-analysis conclusions

the voltages on capacitors can be monitored by j-Fet op amp - but they are changing relatively fast at low capacities ++ the switching adds a settling time for op amp = a dealy before the valid output appears at op amp (may be several microseconds)

another problem is the large inductor with parasitic properties (self-resonance , inter-winding capacitance , core magnetizing time)
https://www.google.com/search?q=per...tization+at+unipolar+excitation&channel=entpr

Ci139, I will draw up a schematic for the sampling of the capacitor voltage using the MCP6002 op amp for supplying an ESP32 and so would appreciate your thoughts on the layout.

 

So here it is. I have added what I think would also help manage the noise for feeding to an ESP32, but this is new territory for me. The various outputs (signal and supplies) would go via a 4-way 'JST' connector to the MCU.

I reasoned that the LD1117 regulator can drop 5V to 3.3V with less waste than going straight from 12V, which I think it can also do.

Any refinements would be appreciated. Thanks

 

Ok, but things might change if resonance is introduced to the series LC circuit, as that will surely change the behaviour of the setup.

Behavior of LC circuit always is the same - converting pulse to sine.

 

Behavior of LC circuit always is the same - converting pulse to sine.
View attachment 366574

Well they say a pulse contains a very large number of different frequency sine waves so I guess in a sense the LC resonance selects from that wide range. I expect also that the pulse version better reflects the burst of charge moving between the two capacitors.

 

Well they say a pulse contains a very large number of different frequency sine waves so I guess in a sense the LC resonance selects from that wide range.

I agree.

I expect also that the pulse version better reflects the burst of charge moving between the two capacitors.

What is difference?

 

I agree.

What is difference?
View attachment 366580

No difference, from the mathematical point of view, between two 100u caps in series compared to one larger one, for resonance frequency, but I was comparing a square wave pulse vs a sine wave generator. There are magnetic field effects in the inductor that vary with di/dt caused by the charge transfer that are likely not to be modelled well at the moment. But that’s for me to explore. Also, the first 100u cap’s charge being released to the second 100u cap is not the same as just having a 50u one. It’s only the same in terms of resonant frequency.

 

No difference, from the mathematical point of view, between two 100u caps in series compared to one larger one, for resonance frequency, but I was comparing a square wave pulse vs a sine wave generator. There are magnetic field effects in the inductor that vary with di/dt caused by the charge transfer that are likely not to be modelled well at the moment. But that’s for me to explore. Also, the first 100u cap’s charge being released to the second 100u cap is not the same as just having a 50u one. It’s only the same in terms of resonant frequency.

Sure, you will obtain unique results, because L1 will instantly lost its energy on every break of SW2.

 

Any refinements would be appreciated. Thanks

U1 is missing an input capacitor, as indicated on the datasheet pages 21-24.

The non-inverting (+) input to U3 does not have a DC reference. It appears that the input circuit is nothing more than a capacitor to GND.

The Input to U1 is not referenced to the same potential as its GND pin. IOW its input is completely floating with respect GND. There is no return current path to the isolated output's "Iso. Gnd". This creates a problem for U3's power connections. To correct this, disconnect U1 pin 3 from ISO 5V and connect it to Vdd 12V

When I searched for "2-1211" on the Traco website, it came up with a part that does not match the pinout in your schematic.

https://www.tracopower.com/sites/default/files/products/datasheets/trs2_datasheet.pdf?t=1777676401

ak

 

The non-inverting (+) input to U3 does not have a DC reference. It appears that the input circuit is nothing more than a capacitor to GND.

U1 is missing an input capacitor, as indicated on the datasheet pages 21-24.

The Input to U1 is not referenced to the same potential as its GND pin. IOW its input is completely floating with respect GND. There is no return current path to the isolated output's "Iso. Gnd".

When I searched for "2-1211" on the Traco website, it came up with a part that does not match the pinout in your schematic.

https://www.tracopower.com/sites/default/files/products/datasheets/trs2_datasheet.pdf?t=1777676401

ak

I attach the data sheet I was using and followed the pin out on the last page - I thought. I will have a look at the issues you mentioned on Monday and re post the schematic.

 

Thanks for the datasheet, it clears up the pinout confusion.

What is the purpose or intent for the galvanically-isolated power source?

ak

 

Thanks for the datasheet, it clears up the pinout confusion.

What is the purpose or intent for the galvanically-isolated power source?

ak

To supply the off board ESP32 which benefits from a ‘quiet’ supply.

 

In order for the ESP32 to interact with this circuit, they both *must* share a common ground. You can get that by tying U2 pin 5 to GND, but now you have an unnecessarily complex power system.

The best way to reduce noise in a system is to not create more of it. You can get a more "quiet" power source by replacing U2 with another 3-terminal regulator. I would go with a switcher only if the required current were so high that power dissipation in a linear regulator became an issue. And even then you would not need a fully isolated 5 v source; a well-filtered buck regulator probably would suffice.

What are the required output currents at 3.3 V and 5 V?

ak

 

To address your first comment in post 32, how do I connect the cap being measured to the op amp, in particular the negative side?

The DUT is one or other of the caps in the original post image, as shown again below.

Regarding U1, dropping 12V to 3.3V is going to generate a lot of unwanted heat, so I'd rather just drop from 5V as shown. I have switched the ground so that U1 has the same ground reference as U2.

 

Use simple setup:
Connect 1 us 100 A pulse current source (FET allows do it) to C1, so you do not need switches.

Every pulse provides step voltage 1 V on C1.

Analyze voltages on C1 and C2:

 

Interesting, but the charge transfer between C1 and C2 is an essential part of the investigation, so resonance issues are only a minor part of it.

 

To address your first comment in post 32, how do I connect the cap being measured to the op amp, in particular the negative side?

As long as there is no other connection between anything in the 30 V circuit and anything in the 12 v circuit, the direct connections you show should work. The DUT will appear to the 12 V circuit as a weird battery, a floating voltage source whose output is all over the place. Ah, but the drive circuit for the two FET switches is a connection. Hmmm . . .

Regarding U1, dropping 12V to 3.3V is going to generate a lot of unwanted heat,

How much?

I have switched the ground so that U1 has the same ground reference as U2.

Closer, but still not there yet. Follow the U3 power path from U1 pin 2 to U3 pin 8; then from U3 pin 4 to "circuit ground", but *not* to U1 pin 1. If you disconnect U3 pin 4 from Circuit Ground and connect it to Iso Gnd, that should fix this portion of things. Now, the only thing the 12 V source *and its return* are connected to is the U2 input stage. Everything else is referenced to ISO Gnd.

In the 30 V circuit, there is a switch between the bottom of C2 and the bottom of B1. That is the problem, and it is not a simple one. Your overall circuit has three separate grounds, plus whatever the gate drive circuit uses. As you are discovering, ground management in data acquisition systems can be a thorny problem. I want to say that I think you need two isolated grounds, one for power and control, and one for signals and measurement. The question is where/how is the drive circuit for the two FETs connected to power, ground, and the gates? If you are using the circuit in post #6, then that GND must be tied to the bottom of battery B1, and the circuit powered by the 30 V. If that is correct, then we're almost there.

ak

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