Modulo-2 count up and down. [Solved]

Thread Starter

Cstp

Joined Feb 19, 2019
9
Hi everyone, I tried to design a modulo-2 to get this sequence 00,01,10,11,01,10,00. But glitch append at the ouput of the XNOR (cd4027) and trig the flipflop

randomly. So do you have any suggestions to design this circuit?
 

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BobTPH

Joined Jun 5, 2013
3,316
A modulo 2 counter would have only 1 bit and there is no difference between counting up and counting down. In other words, a modulo-2 up / down counter is nothing more than a T flip-flop.

Did you perhaps, mean 2's complement rather than modulo-2?

Bob
 

Zeeus

Joined Apr 17, 2019
615
Hi everyone, I tried to design a modulo-2 to get this sequence 00,01,10,11,01,10,00. But glitch append at the ouput of the XNOR (cd4027) and trig the flipflop

randomly. So do you have any suggestions to design this circuit?
Use 3 JK flip flops but with 2 outputs Q1 and Q0

J2 = Q0 * Q1 logic and
K2 = Q1
J1 = Q0
K1 = Q2 + Q0
J0 = Q0' (Q0 inverse)
k0 = Q1' (Q1 inverse)

nowxx.jpg

Produced your counting sequence.
 

dl324

Joined Mar 30, 2015
12,871
Use 3 JK flip flops but with 2 outputs Q1 and Q0
This is in the homework section. We don't do the homework; we offer guidance. Students will learn more that way and can't be accused of cheating.

EDIT: My apologies. It sounded like homework to me and I thought this was in homework help.
 
Last edited:

andrewmm

Joined Feb 25, 2011
1,474
Counters with a decode, will generally give a glitch out as all the bits of the counter will not switch at exactly the same point / speed.

Well done you for detecting and diagnosing the glitch ,

So the answer, is to either remove the glitch, or ignore the glitch ,
You have been shown a way of removing the glitch , a low pass filter
what do you think could be the problems with a low pass filter, think about the frequency spectrum of an edge.

An alternative method,
what time is the glitch in relation to the clock,
think of the timing diagram, is it after or before the clock ?
is it the glitch there for more than one clock ?
 

Thread Starter

Cstp

Joined Feb 19, 2019
9
This is in the homework section. We don't do the homework; we offer guidance. Students will learn more that way and can't be accused of cheating.

EDIT: My apologies. It sounded like homework to me and I thought this was in homework help.
It's not for homework but I should have stayed in school longer lol
 

Thread Starter

Cstp

Joined Feb 19, 2019
9
Use 3 JK flip flops but with 2 outputs Q1 and Q0

J2 = Q0 * Q1 logic and
K2 = Q1
J1 = Q0
K1 = Q2 + Q0
J0 = Q0' (Q0 inverse)
k0 = Q1' (Q1 inverse)

View attachment 230685

Produced your counting sequence.
Thank you very much, I really appreciate it. I will try this circuit soon. But I managed to get my circuit to work. I think my breadborad was causing me the problem.
 

Thread Starter

Cstp

Joined Feb 19, 2019
9
Counters with a decode, will generally give a glitch out as all the bits of the counter will not switch at exactly the same point / speed.

Well done you for detecting and diagnosing the glitch ,

So the answer, is to either remove the glitch, or ignore the glitch ,
You have been shown a way of removing the glitch , a low pass filter
what do you think could be the problems with a low pass filter, think about the frequency spectrum of an edge.

An alternative method,
what time is the glitch in relation to the clock,
think of the timing diagram, is it after or before the clock ?
is it the glitch there for more than one clock ?
Thank you very much, I really appreciate it.
 

Thread Starter

Cstp

Joined Feb 19, 2019
9
A modulo 2 counter would have only 1 bit and there is no difference between counting up and counting down. In other words, a modulo-2 up / down counter is nothing more than a T flip-flop.

Did you perhaps, mean 2's complement rather than modulo-2?

Bob
Yes I make a mistake But you guys correct me and I appreciated. After that I understood that I want to make a modulo 6.
 

Thread Starter

Cstp

Joined Feb 19, 2019
9
Hi C,
Welcome to AAC,
What is the clock rate from the 555 timer,?
Have you tried a short R/C filter on the 4027 output.?
E
Yes I try with filter but I managed to get my circuit to work. I think my breadborad was causing me the problem.
 

Thread Starter

Cstp

Joined Feb 19, 2019
9
Counters with a decode, will generally give a glitch out as all the bits of the counter will not switch at exactly the same point / speed.

Well done you for detecting and diagnosing the glitch ,

So the answer, is to either remove the glitch, or ignore the glitch ,
You have been shown a way of removing the glitch , a low pass filter
what do you think could be the problems with a low pass filter, think about the frequency spectrum of an edge.

An alternative method,
what time is the glitch in relation to the clock,
think of the timing diagram, is it after or before the clock ?
is it the glitch there for more than one clock ?
Thank you that confirm what I think. Thank you I will consider all your advice soon in my next development
 

MisterBill2

Joined Jan 23, 2018
8,787
What the description of the desired output requires is a two-bit binary counter. That can be realized with a single dual flipflop IC such as a CD4013. which is a dual R-S with Trigger input positive logic IC. The source of pulses would be separate, and a 555 timer IC can provide that
 
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