Yes I make a mistake But you guys correct me and I appreciated. After that I understood that I want to make a modulo 6.

According to your count sequence, you are looking to make a 2-bit binary up/down counter that jumps from 3 to 1 when counting down.

 

According to your count sequence, you are looking to make a 2-bit binary up/down counter that jumps from 3 to 1 when counting down.

Actually, it would be a 2-bit binary counter that counts from zero, (00) to 3 (11) and then rolls back to 00.

 

Actually, it would be a 2-bit binary counter that counts from zero, (00) to 3 (11) and then rolls back to 00.

That’s what I thought until I read the sequence again closely...0,1,2,3,1 2,0.
Maybe the TS meant 0,1,2,3,2,1,0

 

Re glitches. Two registers, even in the same package will have different propagation times, if you gate together two or more registers, you will generate a glitch.

 

Re glitches. Two registers, even in the same package will have different propagation times, if you gate together two or more registers, you will generate a glitch.

That isthe reason that I suggested a scheme with no registers and no gates, simply a two stage binary counter.

 

hi,
The TS has solved his problem , it was due to a poor layout on a bread board.
E

 

Re glitches. Two registers, even in the same package will have different propagation times, if you gate together two or more registers, you will generate a glitch.

I'd like to give the designers of SSI logic the benefit of the doubt in that they'll be as competent as designers of billion transistor designs.

Engineers I worked with on billion+ transistor microprocessor designs were very aware of clock skew and took steps to mitigate it (they had to send clocks thousands of microns across the chip and clock tree design was quite involved). If they couldn't control skew, they'd have all sorts of problems with setup and hold time violations.

They and the people who did the actual device layout would have been informed about how to match devices so that flip flops wouldn't switch at different times. When I was working on 90nm or 65nm designs, those of us on the process side made sure that engineers and layout designers knew how to draw devices for the best matching. Wafer level variation can't be controlled as tightly, but in die variations, particularly for designs with only a few dozen gates, should be very small.

EDIT: Should have said that variation in a small region of a die (i.e. for adjacent and "matched" devices) will be small.

If we assume that the designers weren't very diligent in matching device performance, additional gates can be added to the decode logic to eliminate glitch hazards.

You could carry the timing paranoia a step further and add delays to the B input of the OR gate, match delays for the OR gates, and add delays on the counter outputs to equalize delays. This was easy to do in large designs because we had gates of different drive strengths (e.g. 8 different inverter strengths).

 

Propagation delays and varying response times can certainly cause problems for those just starting to design digital logic. Near the start of my engineering career I did run into that problem with a project that used a ripple counter. It was a lesson indeed, fortunately in a one-off assembly.

 

@Cstp To further flog this dead horse, here's an implementation using a mod 6 (first 6 counts) gray code counter, so the only potential for glitches is when the counter rolls over to zero from 7.

I can post the design info for the counter and decoder if you're interested. Sometimes I wish I had stayed in school longer too...

The circuit in post #27 is still more complete because dealing with the glitches in this circuit would require 2 more minterms for the LSB.