Hi,

Please assist. I have attached circuit with many shift registers chained in a line. Also looking to add more of them.

The circuit works, however I am concerned if this is safe and reliable to use like this and also a bit baffled as to why it works ??

The same clock is applied to each shift register and I am wondering if there are possibilities of it going out and other shift registers down the line gets sampled at the wrong time ?

Are there any dangers / risks to this circuit failing to work ?
What can I do to avoid these ?

Thanks !

 

There's a risk of failing if the clock signal isn't buffered. For safety is better buffer this sign.

 

Thank you. How would you recommend I do that ? Can you recommend circuit ?
Do you mean buffer each one before the specific shift registers clock ?

 

Thank you. How would you recommend I do that ? Can you recommend circuit ?
Do you mean buffer each one before the specific shift registers clock ?

You can use some TTL buffer (74LS06 as example) of your preference.

 

Thanks. Do you mind elaborating a bit on the other questions as well.
Do I buffer before each shift register chip or only before main clock ?

 

Thanks. Do you mind elaborating a bit on the other questions as well.
Do I buffer before each shift register chip or only before main clock ?

Each CMOS (or any other logic family) output has a maximum load that it can drive. The load consists of each input and wiring parasitics. Adding more shift registers puts more load to the two clock signals.

You can buffer with any line driver device.

 

Thanks. Do you mind elaborating a bit on the other questions as well.
Do I buffer before each shift register chip or only before main clock ?

I don't know what device is generating the clock sign. What device controls the SHFTCLK and LCH CLK? If one device control SHFT CLK and other device is used to control LCH CLK, make it:

 

It is very unlikely that you need to buffer the clock since there are only six inputs being driven. I certainly wouldn't use one unless there was some compelling reason such as source with exceptionally low drive capability or with slow transitions that would make a Schmitt trigger necessary. If you do use a buffer, don't use any TTL part because the clock inputs are not TTL compatible and using a TTL buffer would make reliability worse, not better.

[EDIT] I missed the bit about adding more shift registers. That may warrant using a buffer. If the layout becomes physically large, there can be issues with ringing on the clock lines if they are long. Sometimes splitting the clock into two or more segments, each with its own buffer, can be useful, BUT you must be careful not to introduce differential delays that would cause violation of data setup and hold times.

What is the purpose of all the pullup and pulldown resistors? The HC595 has tri-state outputs that are permanently enabled, so the pulling resistors do nothing but waste power, as far as I can see.

 

To elaborate a bit on setup and hold times:

In clocked devices, the timing relationship between the active events of the clock and the data that is being "clocked in" must be considered. The HC595 is a "rising edge triggered" shift register. This means that the data must be valid for some time before the clock goes high (setup time) and then remain valid for some time after that transition (hold time). When operating at 4.5 V the setup time is specified as 25 ns minimum and the hold time is specified as 0 ns maximum. This means the serial input data needs to be at a stable logic level for at least 25 nanoseconds before the clock makes the low to high transition, but you can change the data as soon as the clock has reached the logic HIGH level.

Once the clock has made the transition, it will take some time for the data at the outputs of each flip flop, including the last one, to become valid. This propagation delay will also be specified. When you have several shift registers cascaded, you must wait long enough for the data at the output to become stable (the propagation delay time) and then also wait some more time so that that new data has been stable long enough to meet the required setup time for the next stage. This sets the minimum period for the clock (usually; some devices may impose additional minimum times for HIGH level and LOW level). Section 7.6 of the TI datasheet for the HC595 details the timing requirements. Section 9 shows the timing relations.

When you run a common clock to a bunch of shift registers, you need to consider how an delays in the clock due to added buffers or in the connections can impact what is happening. Generally with relatively slow devices like the HC series, connection delays aren't likely to pose a problem if everything is on one circuit board. Buffers can cause problems if not used wisely so that you still maintain very small differences in the time of arrival of the clock at the individual registers. With very fast logic families, the delays in connections must be very carefully evaluated and managed. Even with slower logic, if you had multiple registers spaced far apart, such as on separate PCBs spaced a long way apart, then things can get messy, not only from a timing perspective but a "signal integrity" perspective ("reflections" with long transmission paths, differences in "ground" potentials, etc.), and very great care is warranted.

 

Just a thought but this design in Verilog pretty straightforward. And
those tools examine timing, and possibly put all that logic in a single
part.....

Regards, Dana.

 

I don't know what device is generating the clock sign. What device controls the SHFTCLK and LCH CLK? If one device control SHFT CLK and other device is used to control LCH CLK, make it:

DSPIC30F4013 micro controls all as a SPI interface.

It is very unlikely that you need to buffer the clock since there are only six inputs being driven. I certainly wouldn't use one unless there was some compelling reason such as source with exceptionally low drive capability or with slow transitions that would make a Schmitt trigger necessary. If you do use a buffer, don't use any TTL part because the clock inputs are not TTL compatible and using a TTL buffer would make reliability worse, not better.

[EDIT] I missed the bit about adding more shift registers. That may warrant using a buffer. If the layout becomes physically large, there can be issues with ringing on the clock lines if they are long. Sometimes splitting the clock into two or more segments, each with its own buffer, can be useful, BUT you must be careful not to introduce differential delays that would cause violation of data setup and hold times.

What is the purpose of all the pullup and pulldown resistors? The HC595 has tri-state outputs that are permanently enabled, so the pulling resistors do nothing but waste power, as far as I can see.

The idea of the pullup and pulldown resistors is to have a certain state while the MCU is starting up after reset or power up...

To elaborate a bit on setup and hold times:

In clocked devices, the timing relationship between the active events of the clock and the data that is being "clocked in" must be considered. The HC595 is a "rising edge triggered" shift register. This means that the data must be valid for some time before the clock goes high (setup time) and then remain valid for some time after that transition (hold time). When operating at 4.5 V the setup time is specified as 25 ns minimum and the hold time is specified as 0 ns maximum. This means the serial input data needs to be at a stable logic level for at least 25 nanoseconds before the clock makes the low to high transition, but you can change the data as soon as the clock has reached the logic HIGH level.

Once the clock has made the transition, it will take some time for the data at the outputs of each flip flop, including the last one, to become valid. This propagation delay will also be specified. When you have several shift registers cascaded, you must wait long enough for the data at the output to become stable (the propagation delay time) and then also wait some more time so that that new data has been stable long enough to meet the required setup time for the next stage. This sets the minimum period for the clock (usually; some devices may impose additional minimum times for HIGH level and LOW level). Section 7.6 of the TI datasheet for the HC595 details the timing requirements. Section 9 shows the timing relations.

When you run a common clock to a bunch of shift registers, you need to consider how an delays in the clock due to added buffers or in the connections can impact what is happening. Generally with relatively slow devices like the HC series, connection delays aren't likely to pose a problem if everything is on one circuit board. Buffers can cause problems if not used wisely so that you still maintain very small differences in the time of arrival of the clock at the individual registers. With very fast logic families, the delays in connections must be very carefully evaluated and managed. Even with slower logic, if you had multiple registers spaced far apart, such as on separate PCBs spaced a long way apart, then things can get messy, not only from a timing perspective but a "signal integrity" perspective ("reflections" with long transmission paths, differences in "ground" potentials, etc.), and very great care is warranted.

Thank you. That helps a lot.
I should also mention that my clock speed is < 1MHz. So by the sounds of it it makes sense why my circuit works and in short is should work pretty safe continuously as my PCB is small etc...is this correct ?