Hi,

I am trying to simulate the sequential discharge of 2 capacitor banks into a single RL load. Ideally, capacitor bank 1 should discharge at t=0 and bank 2 will begin to discharge 0.4 ms later. However, the simulation shows that only capacitor bank 1 is active. When both banks are initially charged up to 500V, bank 1 (left) discharges a peak current of ~14.7 kA whereas capacitor bank 2 (right) only discharges a peak current of 130 A. The schematic is attached below. I would greatly appreciate it if someone could identify the problem.

Thank you.

 

hi f20.
This is a modified circuit for debugging purpose only.
It may help.
E

 

The two ends of the bus bar in post #1 are shorted by the two grounds.

 

Hi,

I am trying to simulate the sequential discharge of 2 capacitor banks into a single RL load. Ideally, capacitor bank 1 should discharge at t=0 and bank 2 will begin to discharge 0.4 ms later. However, the simulation shows that only capacitor bank 1 is active. When both banks are initially charged up to 500V, bank 1 (left) discharges a peak current of ~14.7 kA whereas capacitor bank 2 (right) only discharges a peak current of 130 A. The schematic is attached below. I would greatly appreciate it if someone could identify the problem.

Thank you.

See attached.

 

thanks everyone! really appreciate the help in looking through my schematic & modifying it!