Hello everyone,
I am working on LSM6DS3 IMU module interfacing with an Arm Cortex M0 processor. I read the datasheet of two modules, the problem I am facing I didn't understand how I2C communication is defined in the LSM6DS3 datasheet. I attached a reference datasheet. I2C interface define in page no:36
Actually, I want to pull the sensor data from its output registers using ARM Cortex M0 i.e I want to perform a read operation.
In the datasheet, the protocol defined differently that made me confuse more.
Please help on this.
Thank you
vishnu

 

The sensor uses 3.3V.
Is the ARM chip also 3.3V or is it 5V?

 

Hi shteii01,
ARM chip also uses 3.3V only.

 

It is pretty standard I2C and the protocol is similar to an EEPROM where the LSM's registers are like the bytes of the memory.

The device is addressed by sending a Start condition followed by the slave address + Read/Write. Note that the slave address also has one extra bit that corresponds to a package pin (SA0). That allows you to have more than one of these on the bus. You send the slave address (SAD) with read/write indicated and the SUB address in the next byte. The SUB address specifies the register to read or write. Note that like an EEPROM, to read this chip you first must WRITE the SUB address to select the address of the register you want to read from then send a Repeat Start, the slave address again (this time with the R/W bit high to select read), then read the register(s).

The tables beginning on page 36 show the exchange. Consider Table 13. The upper row is what the master does, the bottom row is what the slave does. The columns indicate each operation. In table 12, the master sends ST, then SAD+W (slave address + write). The slave then performs SAK (the I2C ACK). Master sends SUB, slave ACKs. Master sends the first DATA byte, slave ACKs. Master sends next DATA byte, Slave ACKs. Master sends SP (stoP condition) to terminate the transaction.

Table 15 shows a multi byte read. Master sends STart then SAD (slave address +Write). Slave ACKs. Master sends the SUB address, slave ACKs. Now the internal address pointer is selecting the register(s) to read. But, the mode is still WRITE so the master has to change that. It does it by sending another STart (called a repeat start since there was no stoP condition). As before, the master sends the slave address + READ (SAD+R) and the slave ACKs. Now the master can clock in the register bytes beginning at the address set in the first part. Note that as each byte is received, the master must acknowledge the slave (MAK). That tells the slave that the master will be reading more byte(s). This continues until the master has read the last byte then it sends a NAK (NMAK) to tell the slave to release the I2C bus. The master then sends stoP to complete the transaction.

ST is using non-standard terminology here which adds some confusion. The attached I2C spec gives complete info on I2C. You should know it by heart.

That's how the bytes get back and forth. What the bytes actually mean is what the other 100 pages of the datasheet is all about

Good luck.