# LOGISM FREQUENCY COUNTER

#### nanor123

Joined Jul 29, 2022
7
Im trying to make a frequency counter using logism. I have successfully made a decade counter using the provided counter in the library which counts up to 999. My issue now is that I cannot make the said decade counter display the Frequency of my inputted signal. I am confused to how I can make the circuit stop counting after 1 second has passed. Any suggestions?

#### ericgibbs

Joined Jan 29, 2010
18,637
Hi 123,
Welcome to AAC,
E

#### nanor123

Joined Jul 29, 2022
7
Hi 123,
Welcome to AAC,
E

This is what I have so far

#### dl324

Joined Mar 30, 2015
16,669
I am confused to how I can make the circuit stop counting after 1 second has passed. Any suggestions?
As this is schoolwork, you need to show us your attempts before we're allowed to give you hints.

#### nanor123

Joined Jul 29, 2022
7
As this is schoolwork, you need to show us your attempts before we're allowed to give you hints.
Ive tried several version of the circuit but it always ends up with me not being able to count the frequency. Part of it is the fact that I've only used logism for 1 week. However I have already created a frequency counter using Proteus but I have issues implementing the same circuit due to the lack of components in logism. Here is my previous attempt. I dont really have a lot of pictures because I've deleted majority of the failed circuits that I have tried. My initial idea was to use a different clocks but I've noticed that when I change the hz for 1 clock it changes for all the clocks so I was left at a deadend.

#### Papabravo

Joined Feb 24, 2006
20,990
I cannot tell what the blocks represent. If they are 4-bit binary counters then eleven of them means your head is in a very dark place. It should take only three 4-bit counters to represent 3 decimal digits. If you use decade counters it should take only three of those. I have no idea WTF you diagram in post #5 is all about.

If you use binary counters then you need to fabricate a binary to BCD conversion before going to the 7-segment displays.

#### nanor123

Joined Jul 29, 2022
7
I cannot tell what the blocks represent. If they are 4-bit binary counters then eleven of them means your head is in a very dark place. It should take only three 4-bit counters to represent 3 decimal digits. If you use decade counters it should take only three of those. I have no idea WTF you diagram in post #5 is all about.

If you use binary counters then you need to fabricate a binary to BCD conversion before going to the 7-segment displays.
That was my previous attempt which I scrapped because as you said it was too complicated I have replaced it already as seen in post number 3. The problem I am now facing is being unable to turn the counter into a frequency counter.

#### Papabravo

Joined Feb 24, 2006
20,990
That was my previous attempt which I scrapped because as you said it was too complicated I have replaced it already as seen in post number 3. The problem I am now facing is being unable to turn the counter into a frequency counter.
Never mind complicated, it would never have worked.
OK. So counters are usually designed to do one single function on each rising clock edge, including:
1. Count, up or down by 1.
2. Load a new value into the counter.
3. Clear to all 0's, or SET to all 1's.
4. Hold the present value for 1 clock cycle.
You choose the counter you wish to use by making a determination if is has the features that you need. If the basic counter building block you choose does not have the features that you need then you need to select a different part or find a work around.

If the basic building block for your counter does not have the "Hold Present Value" function, then an odious alternative is to inhibit the clock for as may cycles as you need to. This technique is referred to a clock gating. It is usually a bad idea in any synchronous system to arbitrarily disable and reenable the clock.

#### dl324

Joined Mar 30, 2015
16,669
My initial idea was to use a different clocks but I've noticed that when I change the hz for 1 clock it changes for all the clocks so I was left at a deadend.

#### nanor123

Joined Jul 29, 2022
7
If the basic building block for your counter does not have the "Hold Present Value" function,
Never mind complicated, it would never have worked.
OK. So counters are usually designed to do one single function on each rising clock edge, including:
1. Count, up or down by 1.
2. Load a new value into the counter.
3. Clear to all 0's, or SET to all 1's.
4. Hold the present value for 1 clock cycle.
You choose the counter you wish to use by making a determination if is has the features that you need. If the basic counter building block you choose does not have the features that you need then you need to select a different part or find a work around.

If the basic building block for your counter does not have the "Hold Present Value" function, then an odious alternative is to inhibit the clock for as may cycles as you need to. This technique is referred to a clock gating. It is usually a bad idea in any synchronous system to arbitrarily disable and reenable the clock.
I see duly noted I shall make revisions thank you

#### nanor123

Joined Jul 29, 2022
7

#### nanor123

Joined Jul 29, 2022
7
Hello I was somehow able to build a frequency counter but now another issue popped out. Every time change to a certain frequency, I also have to change the LOW DURATION of my enable clock to the same value of that frequency. Is there a less hassle way of configuring my enable clock or is this just something I have to deal with?
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#### Papabravo

Joined Feb 24, 2006
20,990
The enable time should ALWAYS be fixed and the result scaled accordingly.

#### dl324

Joined Mar 30, 2015
16,669
I was somehow able to build a frequency counter but now another issue popped out.
If you print to PDF and post a clip from it, you can post a black and white schematic without the useless grid: