Ahh ok, thank you

bro send the final answer


Mod:Created a new thread, previous thread starter not logged in since 2022.

 

The 7447 needs 1,2,3,4,5,6.
This counter makes 0,1,2,3,4,5,6.
Think about moving t1 from Q to /Q. (the other output) This way on reset the output=001b. next clock 010b, Now it should count 1,2,3,4,5,6.
There are probably other things to think about but first try to make a counter work.

 

bro send the final answer

That's not how Homework Help works -- this isn't the place to come if all you want it to have someone help you cheat.

You are expected to show YOUR best attempt to solve YOUR assigned problem. We will then help you discover where you are going astray and help you get back on track and make progress.

 

The 7447 needs 1,2,3,4,5,6.
This counter makes 0,1,2,3,4,5,6.
Think about moving t1 from Q to /Q. (the other output) This way on reset the output=001b. next clock 010b, Now it should count 1,2,3,4,5,6.
There are probably other things to think about but first try to make a counter work.
View attachment 353828

I'm not following the reasoning here.

First, I'm not sure about exactly what change you are proposing. What does "moving t1from Q to /Q" actually mean in this circuit? Is the count value still the three Q outputs shown at the top, or is it [T3,T2,T1]? Is each FF's clock input still connect to the /Q output of the prior FF? Or is the middle one now driven by the Q output of the first one? Does the AND gate still act on the three Q outputs? Or does it now act on the /Q output of the left FF?

I'm guessing (and that's largely what it is) that what you meant was the following:



Ignoring the implications for the reset, the only results in the count starting at 001 if the t1 is used as the lsb of the output, so let's consider the output sequence (again, ignoring where the reset happens).

The basic underlying counter is still a binary ripple counter, so it will count in binary. But the output will have the lsb inverted. So the actual count sequence will be the second column below:

000 --> 001 (1)
001 --> 000 (0)
010 --> 011 (3)
011 --> 010 (2)
100 --> 101 (5)
101 --> 100 (4)
110 --> 111 (7)
111 --> 110 (6)

Since the object is to generate a random value, the fact that the output sequence isn't in binary order is probably not a big deal. But the fact that the six values you want to cycle around are not contiguous is a pretty significant issue.

Then there is the issue of when the reset will actually happen. Since the reset logic is asynchronous, if the outputs pass through the reset target while they are changing, a reset will likely happen at that point. Since this is a ripple counter, the sequence of states that the output goes through is deterministic, but it MUST be considered.

 

I'm not following the reasoning here.

Sorry I thought I had an ideal. Not right.

SN74xx163A 4-Bit Synchronous Binary Counter with load.
Set the inputs to 001b and "load" not "reset". This should start the count out at 1. (d,c,b,a=0001)
Do you have a model for a loadable counter?

 

The thread this post was originally in was for using D FF.

How to create a digital dice circuit on Logism using a 7 segment and D flip flops | All About Circuits

 

Sorry I thought I had an ideal. Not right.

SN74xx163A 4-Bit Synchronous Binary Counter with load.
Set the inputs to 001b and "load" not "reset". This should start the count out at 1. (d,c,b,a=0001)
Do you have a model for a loadable counter?
View attachment 353840

Hi,

After seeing this it would seem to be a good idea to look for a minimum gate design.
Just for one simple idea, maybe...
We know it's easy to reset to state 000 binary from state 111 binary. That gives us a count from 0 to 6 which is 000 to 011 binary. If we can reset to 0 and then force one extra count, this will lead to a count sequence from 1 to 6 which seems to be the desired result.

One thing that comes to mind is to use a one-shot to generate a second pulse right after the reset pulse. The one-shot pulse can be OR'd with the clock pulse. This would require a simple 3-bit UP counter, a one shot, an OR or NOR gate (or possibly an AND or NAND gate), and the usual clock gates and the usual clock enable logic.
There are other ways to get that 2nd pulse also such as simple short delay logic (at state 000) along with the OR'ing with the clock pulse.

Of course another simple idea is to allow a count from 0 to 5 (reset on state 011 binary) and then just use a 3 bit adder to add 1 to the count which provides a count from 1 to 6 inclusive.

Lastly, we can use regular boolean logic to convert the count from 0 to 5 into 1 to 6 and reset to 000 on the input count of 110:
bit 0: a'(c' + cb')
bit 1: c'b'a+c'ba'+cb'a
bit 2: c
where
a' is NOT a
b' is NOT b
c' is NOT c
You can double check those logic statements to make sure they are correct, and if not, correct them.

 

Hi,

After seeing this it would seem to be a good idea to look for a minimum gate design.
Just for one simple idea, maybe...
We know it's easy to reset to state 000 binary from state 111 binary. That gives us a count from 0 to 6 which is 000 to 011 binary. If we can reset to 0 and then force one extra count, this will lead to a count sequence from 1 to 6 which seems to be the desired result.

One thing that comes to mind is to use a one-shot to generate a second pulse right after the reset pulse. The one-shot pulse can be OR'd with the clock pulse. This would require a simple 3-bit UP counter, a one shot, an OR or NOR gate (or possibly an AND or NAND gate), and the usual clock gates and the usual clock enable logic.
There are other ways to get that 2nd pulse also such as simple short delay logic (at state 000) along with the OR'ing with the clock pulse.

Of course another simple idea is to allow a count from 0 to 5 (reset on state 011 binary) and then just use a 3 bit adder to add 1 to the count which provides a count from 1 to 6 inclusive.

Or, instead of chasing down a bunch of pesky timing and glitch gremlins, it could just be designed properly in about ten minutes with a fully-synchronous state machine involving two dual-DFF (74xx74) and two quad-NAND (74xx00) packages.

 

Or, instead of chasing down a bunch of pesky timing and glitch gremlins, it could just be designed properly in about ten minutes with a fully-synchronous state machine involving two dual-DFF (74xx74) and two quad-NAND (74xx00) packages.

Sounds good, maybe at some point you can show the circuit.

 

Sounds good, maybe at some point you can show the circuit.

Not directly, at least not for some time. Remember, this is Homework Help, not Homework Solutions Served on a Silver Plate.

 

homework

Look at your counter. Right now, it starts out counting from 0. Reset causes all the FFs to go to 0. With a simple change you can have it start out counting at 1.
If you can't see it, think about "R" and "S".

 

Not directly, at least not for some time. Remember, this is Homework Help, not Homework Solutions Served on a Silver Plate.

Yes of course, but after a time has passed sometimes members post a solution. Usually after it is clear that the original asker has stopped coming back to the thread.