OK, so I have the Window Comparator, and a delay on the Vlo threshold. That should allow startup/power-up delay.

But V_notfault is still 0V right at start up; so won't any latch circuit immediately occur?

The circuit below is also using the LM339. And it's working. Has it something to do with the circuit below using a pull-up..?

 

I have this. It appears to be working. But I can't say I love it...

I don't understand why the resistor values for R3 and R6 either make or break or the circuit.

And I don't think that LED will light up with such little current.

I also fear that R3 will affect the voltage from the sensor. LTSpice says they match (V(n002) and V(vsensor)) until the trip happens; so it appears OK.

I'm interested in any improvements guys!

 

Here's my modified circuit from post #13 using an LM393:
I added a Reset signal so the circuit starts out in the unlatched state.
It that what you wanted?

 

@crutschow That looks awesome! Can that be applied to the 'Window Comparator' easy enough?

 

Can that be applied to the 'Window Comparator' easy enough?

Can what be?

What do you want the window comparator to do differently form the circuit in post #23?

 

Would something like this work?
First half of the LM393 provides the turn on delay and S1 provides a manual reset after the circuit is latched.

 

Here my suggestion.
I used a CD4093B to make latch.
R1-R3 will need to change to the closest available values.

 

Here my suggestion.
I used a CD4093B to make latch.
R1-R3 will need to change to the closest available values.

I really like this. And the simulated sensor signal is cool too.
I'll have to see what SMD ICs there are for SR or NAND gates.
Question; are the 10k input resistors, or 1Meg feedback resistors necessary? It seems to function without them.

 

Question; are the 10k input resistors, or 1Meg feedback resistors necessary? It seems to function without them.

Hi mrik,
Question for you,
What do you think is the purpose of those 10k's and 1meg's in the circuit, what is their effect.?
E

 

Hi mrik,
Question for you,
What do you think is the purpose of those 10k's and 1meg's in the circuit, what is their effect.?
E

Well. Ummm...

• The feedback resistor could be for hysteresis? To stop chattering close to the trip point? Is that a problem though with the NAND/SR use? Once it latches, it doesn't matter what the Comparator is doing...
• The input resistors I guess are for managing current into the Comparator? But I already have resistors being used for the voltage dividers...
• I can only see a possible requirement for a resistor on the Vout of the current sensor; that might need current limiting.

Or is there some other fundamental design need for them?

 

Here's my latest offering, using a window comparator.

R5/C1 provide a latch hold-off delay during start-up conditions. I've assumed a 1ms rise time for V+ and the high/low reference voltages.
Q1/2 provide the latching function.
The input signal phase was set to show the comparator trip occurring when the lower reference was crossed. J1/2 represent allowance for a trim resistor if required, to cope with component tolerances.

 

There are a number of voltage comparators on the market that have a reference and a latch. Some are used to monitor power supplies. Here is one that I use. In this family there is 1 or 2 comparators and the output can be "OC" or push-pull. Also you have a choice of Q or /Q output.

See MIC833,

 

Well. Ummm...

• The feedback resistor could be for hysteresis? To stop chattering close to the trip point? Is that a problem though with the NAND/SR use? Once it latches, it doesn't matter what the Comparator is doing...

Yes...for hysteresis. A slow moving signal isn't a problem for the schmitt gates, but without it, the comparators can oscillate, become noise generators, and get hot.

• The input resistors I guess are for managing current into the Comparator? But I already have resistors being used for the voltage dividers...

The resistors are required for implementing hysteresis. But we also want to keep the resistor divider load to a minumim and keep the reference voltages as stable as possible. You might want to add a small cap (0.1u) to each divider leg.

• I can only see a possible requirement for a resistor on the Vout of the current sensor; that might need current limiting.

I don't think that is necessary.

 

@ronsimpson Thanks. Yeah I saw those, but I want the current sensor isolated from the uC. Hence I like the Hall Effect sensor ICs. I just haven’t found one that has a latch built in.

 

I really like this. And the simulated sensor signal is cool too.
I'll have to see what SMD ICs there are for SR or NAND gates.
Question; are the 10k input resistors, or 1Meg feedback resistors necessary? It seems to function without them.

The resistors implement hysteresis.
The comparators will function without hysteresis, but their reliability will be questionable, escpecially with a slow changing signal.
See post #33.

 

Thanks @eetech00. So at a minimum I should add a resistor on the non-inverting input and a feedback resistor?

Is it OK to leave the inverting input without one?
Just trying to keep component count down.

 

Thanks @eetech00. So at a minimum I should add a resistor on the non-inverting input and a feedback resistor?
View attachment 259738
Is it OK to leave the inverting input without one?
Just trying to keep component count down.

Yes. but I'd leave the others in.

 

@eetech00 I added a 20mV noise to the signal (datasheet says there is), and I can see why hysteresis is important to manage.

 

Hey Guys; this could possibly be another question - but what is the best way to kill the ZCD signal when a FAULT signal has latched. ZCD is normally HIGH and sends low pulses. I think when a FAULT is latched, I just want to keep the ZCD pin HIGH.

I have this


But that means I am always powering the NPN base under normal conditions. I feel as though, to save power, it should be positioned elsewhere, and only enabled when there is a FAULT?

 

Hey Guys; this could possibly be another question - but what is the best way to kill the ZCD signal when a FAULT signal has latched. ZCD is normally HIGH and sends low pulses. I think when a FAULT is latched, I just want to keep the ZCD pin HIGH.

Maybe this:
You have 2 unused NAND gates leftover.