Hi.A simple SR latch has the issue that if both set and reset are 1 the state of Q becomes undefined since it relies on which side wins the battle of trying to set Q = 0 or 1.

However if instead of 2 pins S and R independent of each other, the NOR or NAND gate which was connected to either Q or Q' input which is not part of the feedback path(since Q is fed into the input for Q' and vice versa) was NOR of SR so instead of S and R pins we had S or R pin and a NOR(S,R) wouldnt that force 2 memory conditions(remove the problematic case of S=1,R=1)?

 

It certainly would change things, BUTat least one RS FF handles it very well alreadty. In that case, with R and S both high, it has both "Q"and "Q-"high. It works for me.

 

Hi.A simple SR latch has the issue that if both set and reset are 1 the state of Q becomes undefined since it relies on which side wins the battle of trying to set Q = 0 or 1.

However if instead of 2 pins S and R independent of each other, the NOR or NAND gate which was connected to either Q or Q' input which is not part of the feedback path(since Q is fed into the input for Q' and vice versa) was NOR of SR so instead of S and R pins we had S or R pin and a NOR(S,R) wouldnt that force 2 memory conditions(remove the problematic case of S=1,R=1)?

First off, in the NAND-based RS latch shown, if both set and reset are 1, then the latch just sits there holding it's current state.

The problem is when both set and reset of 0. That forces both latch outputs to go HI, but that's not the real problem and your solution does nothing to address that real problem.

Say that both inputs are 0. Regardless of what the latch outputs are as a result, what should the latch do if S is taken to 1 some time before R is taken to 1? What should the latch do if the R is taken to 1 some time before the S is taken to 1?

If it shouldn't do the same thing, then the behavior when going from both inputs 0 to both inputs 1 depends on the order in which the two inputs actually change, which means that you have a critical race and a window of time in which if both inputs are relaxed (taken HI), the state of the latch is indeterminate.

 

The correct circuit is:



When S=R , this circuit stores the last values for Q and Q' , when S=1 and R=0 Q becomes 1 and Q' becomes 0 and when S=0 and R=1 Q becomes 0 and Q' becomes 1.I suggest you run this circuit on Logisim or Proteus to confirm for yourselves.

 

NOW I am asking if this question is about an actual available part?? Or is it about a "textbook part"??
OR a science fair project part??
At least the CMOS CD4013, and MC14013 dual RS flipflops seem to have handled it in a very satisfactory manner for a whole lot of years. I have not done much with TTL or ECL components so I can't comment on how they handle the case. (Remark DEleted)

 

The correct circuit is:

View attachment 365581

When S=R , this circuit stores the last values for Q and Q' , when S=1 and R=0 Q becomes 1 and Q' becomes 0 and when S=0 and R=1 Q becomes 0 and Q' becomes 1.I suggest you run this circuit on Logisim or Proteus to confirm for yourselves.

It still has the same fundamental critical race.

In the original latch, the state of the outputs is well-defined when both S and R are asserted (which means when they are LO) -- both Q and Q' are HI. No ifs, ands, or buts about it. The indeterminism comes if both S and R are relaxed simultaneously. THAT is when this 'battle' you refer to happens. The final state of the latch will depend on which side wins the critical race. As long as one input is relaxed sufficiently long (which is measured in nanoseconds) before the other, the behavior is well-defined. It's only within that tiny window that non-determinism rears it's ugly head. But it is fundamental to the behavior when you have two inputs that are telling it to do different things. Which one it listens to depends on which one tells it last.

The same is true with your modified circuit. You still have two inputs that are telling the latch to do different things. If they are both relaxed at the same time, then the final state of the latch is indeterminate because there is a critical race involved.

Be sure that you understand that there are TWO issues here. The first is the state of the latch when both control signals are asserted. In the original latch, they are well-defined but happen to not be the opposite of each other. There is no non-determinism involved in this issue. The second is that the state of the latch when both control signals are relaxed simultaneously is indeterminate because of a critical race.

Your circuit address the first issue to the degree that the latch outputs will always be opposite each other (in steady state), but it introduces a SECOND critical race. If both inputs are asserted at the same time, the state of the latch is indeterminate (though the outputs will be opposite each other, whatever that state turns out to be), and again when both inputs are relaxed simultaneously the state of the latch is once again the result of a critical race.

 

This conflict was probably one of the motivations for the creation of the "J K" type of flip-flop device.
ALSO, it seems like the references often apply to "low-true" logic functions, rather than the "high true" CMOS devices that I have always used.
I suppose that at some point there was an actual benefit with "low true" logic inputs, but it always seems that there is a difficulty seeing the difference between "ZERO"and "Nothing." ( "Nothing" beeing a fault condition, not a valid logicstate.)

 

NOW I am asking if this question is about an actual available part?? Or is it about a "textbook part"??
OR a science fair project part??
At least the CMOS CD4013, and MC14013 dual RS flipflops seem to have handled it in a very satisfactory manner for a whole lot of years. I have not done much with TTL or ECL components so I can't comment on how they handle the case. (Remark DEleted)

No I designed it for fun.I just didnt like there was a fault condition on something like the SR latch which I like more than flip flops because I like asynchronous devices.

 

This conflict was probably one of the motivations for the creation of the "J K" type of flip-flop device.
ALSO, it seems like the references often apply to "low-true" logic functions, rather than the "high true" CMOS devices that I have always used.
I suppose that at some point there was an actual benefit with "low true" logic inputs, but it always seems that there is a difficulty seeing the difference between "ZERO"and "Nothing." ( "Nothing" beeing a fault condition, not a valid logicstate.)

What do you mean by that?

 

What do I mean by what?? The creation of the JK FF? or the reference to "Low True" logic?? Or the "ZERO versus Nothing statement?? I made several assertions in post #8. Which one are you asking about????
The function of the JKFF allows for synchronous logic to change state with a "CLOCK" pulse, avoiding logic race problems.
"LOWTRUE" logic uses the lower level voltage as the active state.
"Zero" versus "Nothing" is the quandry arising when a failed connection produces a signal identical with an actual data state. I believe that is the reason we have analog current loops using four to 20 milliamps instead of zero to 20 milliamps, since an open connection will also produce a zero current condition. In many control systems it is vitally important to know when some connection has failed.

 

What do I mean by what?? The creation of the JK FF? or the reference to "Low True" logic?? Or the "ZERO versus Nothing statement?? I made several assertions in post #8. Which one are you asking about????
The function of the JKFF allows for synchronous logic to change state with a "CLOCK" pulse, avoiding logic race problems.
"LOWTRUE" logic uses the lower level voltage as the active state.
"Zero" versus "Nothing" is the quandry arising when a failed connection produces a signal identical with an actual data state. I believe that is the reason we have analog current loops using four to 20 milliamps instead of zero to 20 milliamps, since an open connection will also produce a zero current condition. In many control systems it is vitally important to know when some connection has failed.

What do I mean by what?? The creation of the JK FF? or the reference to "Low True" logic?? Or the "ZERO versus Nothing statement?? I made several assertions in post #8. Which one are you asking about????
The function of the JKFF allows for synchronous logic to change state with a "CLOCK" pulse, avoiding logic race problems.
"LOWTRUE" logic uses the lower level voltage as the active state.
"Zero" versus "Nothing" is the quandry arising when a failed connection produces a signal identical with an actual data state. I believe that is the reason we have analog current loops using four to 20 milliamps instead of zero to 20 milliamps, since an open connection will also produce a zero current condition. In many control systems it is vitally important to know when some connection has failed.

I like asynchronous devices thats all and the SR flip flop is a asynchronous memory element BUT it is guaranteed to have a unstable condition so I modified it a bit so there is no unstable condition.Also it is obviously a HIGH TRUE logic device(even after the changes) and for the second question I dont know the answer to your question.I have designed as a digital circuit not as a sum of transistors but I guess the simplest case is to make Nothing = Zero.

 

At least in the CMOS IC logic realm the FF products are not unstable. At least not the common dual flipflops, specificly the 4013 and 4027 BOTH have well defined statesfor set, reset, and both R and S at the same time. In addition, they both work in the clocked and data modes.
AND, as to asynchronous devices, try designing a multi digit adder circuit with asynchronous digital logic ICs. Clocked logic was not created on a whim, it was done out of necessity.

 

NOW I am asking if this question is about an actual available part?? Or is it about a "textbook part"??
OR a science fair project part??
At least the CMOS CD4013, and MC14013 dual RS flipflops seem to have handled it in a very satisfactory manner for a whole lot of years. I have not done much with TTL or ECL components so I can't comment on how they handle the case. (Remark DEleted)

Somewhat apples and oranges -- the CD4013 and MC14013 are both edge-triggered flip flops as opposed to a non-clocked latch. They serve different purposes and have their own sets of advantages and disadvantages relative to the other.

 

This conflict was probably one of the motivations for the creation of the "J K" type of flip-flop device.
ALSO, it seems like the references often apply to "low-true" logic functions, rather than the "high true" CMOS devices that I have always used.
I suppose that at some point there was an actual benefit with "low true" logic inputs, but it always seems that there is a difficulty seeing the difference between "ZERO"and "Nothing." ( "Nothing" beeing a fault condition, not a valid logicstate.)

Active-LO (what you are calling "low-true") have advantages and disadvantages, like most things in engineering. In most logic families it is easier to sink current than source it, so if you are driving many inputs in parallel, which if often the case is larger designs, you can drive bigger loads or get greater fanout with active-LO logic. Also, the internal logic is often simpler, and hence cheaper/faster, with active-LO logic.

The issue with the fault state is there regardless of whether you are using active-LO or active-HI signaling. In either case, if you want to detect it you need additional effort. What it really comes down to is how you want the system to behave in the case of that kind of fault and designing the circuit accordingly -- sometimes active-LO has the fault behavior you want, other times it is exactly what you don't want. But the same is true for active-HI signals, too.

 

I like asynchronous devices thats all and the SR flip flop is a asynchronous memory element BUT it is guaranteed to have a unstable condition so I modified it a bit so there is no unstable condition.Also it is obviously a HIGH TRUE logic device(even after the changes) and for the second question I dont know the answer to your question.I have designed as a digital circuit not as a sum of transistors but I guess the simplest case is to make Nothing = Zero.

A lot of people like asynchronous logic because it lets them be more ad hoc in their design approach, which is another way of saying that they don't want to bother with actually designing their logic systematically up front but, instead, want to wing it as they go. But asynchronous logic design is not for the feint of heart -- there are demons that hunt those waters. Unless you are willing to commit to doing a proper analysis of your logic and the specific implementation of it to ensure that there are no critical races or timing hazards, you should not be doing asynchronous logic. I have seem numerous designs fail, sometimes dangerously, because the designer threw together some logic that relied on gated clocks and using the clear and preset inputs of the flip flops without bothering to carefully assess whether there are any glitch hazards. The reality is that there almost always are, and dealing with them is not always easy.

 

ALL

Somewhat apples and oranges -- the CD4013 and MC14013 are both edge-triggered flip flops as opposed to a non-clocked latch. They serve different purposes and have their own sets of advantages and disadvantages relative to the other.

BOTH the 4013 seriesAND the 4027 series of FF devices have, IN ADDITION TO THE "CLOCK" and "DATA" inputs, also non-edge triggered SET and RESET inputs. AND, for both models, a high on SET provides a high on Q, and even at the same time, a high on RESET provides a high on Q^. (Qnot). My font set does not include logic symbols.
The fact that both offer clocked data inputs does not alter the S/R operation at all. Just be sure to terminate all inputs for CMOS.

 

At least in the CMOS IC logic realm the FF products are not unstable. At least not the common dual flipflops, specificly the 4013 and 4027 BOTH have well defined statesfor set, reset, and both R and S at the same time. In addition, they both work in the clocked and data modes.
AND, as to asynchronous devices, try designing a multi digit adder circuit with asynchronous digital logic ICs. Clocked logic was not created on a whim, it was done out of necessity.

The behavior of the CD4013 when both S and R are asserted has the exact same issue that the basic RS Latch circuit has, namely that both Q and Q' outputs are driven HI at the same time, which can cause problems with the larger design if it does not allow for the possibility that Q and Q' may not always be opposite (except during actual transitions).

As for "stability", which I'm assuming from the discussion context refers to nondeterministic behavior, the CD4013 has the same non-determinism and for the same reason.

If both R and S are asserted and then both are de-asserted nominally at the same time, what should the output be? It comes down to which one wins the race to be seen by the internal logic as having been de-asserted later than the other one. Also, if the asynchronous input (set/clear) does not satisfy the removal time relative to the clock, the behavior is non-determinate.

The fact that all of these parts have things like set up and hold time specifications is precisely because of the critical races that come into play if they are violated. That is no different than the basic RS latch circuit -- if it is not operated properly, it's behavior is non-deterministic because it has been forced into a region where critical races come into play. In either case, it is up to the design to ensure that these specifications are met.

 

ALL

BOTH the 4013 seriesAND the 4027 series of FF devices have, IN ADDITION TO THE "CLOCK" and "DATA" inputs, also non-edge triggered SET and RESET inputs. AND, for both models, a high on SET provides a high on Q, and even at the same time, a high on RESET provides a high on Q^. (Qnot). My font set does not include logic symbols.
The fact that both offer clocked data inputs does not alter the S/R operation at all. Just be sure to terminate all inputs for CMOS.

Which means that if both SET and RESET are asserted at the same time, that the Q and Q' outputs are the same. This can cause problems if it is not allowed for. And this is EXACTLY the same situation as with the basic RS latch.

And this dodges what the "well-defined behavior" when SET and RESET are relaxed at the same time. What are the Q and Q' outputs when we go from SET=RESET=1 to SET=RESET=0?

It is indeterminate, just as with the basic RS latch.

 

There is no way to "fix" the anomaly of an S-R flip-flop.

Here is your basic S-R flip-flop. I have intentionally labelled the outputs as X and Y and not Q and /Q in order to avoid any false assumptions.

We can show the truth-table as follows:

S1	S2	X	Y
0	0	1	1
0	1	1	0
1	0	0	1
1	1	PREVIOUS STATE	PREVIOUS STATE

Notice that the outputs X and Y change when the inputs S1 and S2 are ACTIVE-LOW.

We can reverse the logic of S1 and S2 by inserting inverters after S1 and S2.


The truth-table is now changed as follows:

S1	S2	X	Y
0	0	PREVIOUS STATE	PREVIOUS STATE
0	1	0	1
1	0	1	0
1	1	1	1

Edit: "PREVIOUS STATE" is meant to mean when the inputs change from 01 or 10 to 00. In other words, only one input is allowed to change state. If both inputs change from 1 to 0, we have an "indeterminate result".

The apparent inconsistent behaviour occurs when inputs S1 and S2 both simultaneously change from HIGH to LOW. As already explained, this introduces a "race" problem when one input could lag behind the other. The last one wins. If both inputs change at exactly the same time, there is no guarantee on the outcome of the flip-flop.

CLOCKED S-R FLIP-FLOP

You can create a clocked S-R flip-flop by adding a CLOCK input via S3. However, this does not solve the "race" problem when both S1 and S2 are set to HIGH.

 

The bad news is that to create a succesful design using real-world IC devices one must understand the limitations, and allow for them. THAT probably has a lot to do with the number of folks unable to design digital circuits that perform as intended. I have never had problems with R/S FFs because of that limitation.

SEriously!, there is a valid reason that the manufacturers of those digital logic IC devices publish those data sheets with all of those boring numbers on page after page. ALL of their production facilities are located in THE REAL WORLD, which means they suffer from real world limitations. This places a burden on all of those folks who choose to be logic hardware circuit designers: They can only use real world components! Finite propogation delays and setup times.
AND the insidetheblock circuits for logic circuits shows us that they are not as simple inside as it seems. THAT part is where the long explanation gets really technical, and talks about details that are seldom discussed.

DATA SHEETSare our friends!! They keep those of us who study them from looking like we have no clues.