OK. So whats the benefit of 120vAC in to get 120vAC out? Or have I missed something?Hi,
I am getting AC via an isolation transformer but it is still 120VAC. I only have those 2 small capacitors for filtering but they are mostly place holders for the PCB as I am using 5.4uF on the prototype board. With no/light load the rectified signal had surprisingly small amount of ripple(obviously this will go up with more load). but yes the rest is correct.
This is a good example of where a seemingly simple schematic hides a whole world of potential pain. Consider this partial schematic, where I've inserted some of the 'real-world' parasitic inductances & capacitances into the simple schematic from post #19.Can you elaborate on the
" You're right about the layout of the source connection being complex though. its important that the hi-side source to low-side drain and the output is separate from the gate-source circulating current."
Are these two sentences related? how is the Source complex? should I be "grounding" the two Sources to each other and thats it? And for the second sentence, is that something I should be doing in the schematic or more so something to do with PCB layout because I do not really understand what I would do to change the schematic.

Remember we're trying switch the MOSFET Q1 on and off as quickly as possible to minimise switching losses. That means we have fast rise time (= high frequencies), high current, switching transients circulating in the HO->gate->source->VS loop, as well as Vsupply->drain->source->out->Gnd loop. Several possible actions could occur, all potentially detrimental. Firstly the gate parasitic inductance L(g-para) can slow the rise time, slowing turn on, then as drain-source current starts to flow the source parasitic inductance L(s-para) tries to resist that reducing gate-source voltage, slowing turn on as well, especially if the VS connection is any distance from the source pin on the output path. Further problems can arise as parasitic capacitances couple with the parasitic inductances to produce phase shifts which if the total loop shift is close to 360degrees will induce ringing or, worst case, outright oscillation at various frequencies- which can be highly damaging to both MOSFET and driver. These can be very hard to diagnose as even approaching them with a 'scope probe can shift parameters far enough to quench them. 20nH isn't much inductance, but that's roughly 2cm of PCB track. Some solutions to this include keeping gate drive paths as short and fat as possible (easier said than done with highly-integrated driver chips), avoiding ground planes under gate drive paths, and care with routing.
Which brings me to your point about the schematic. In days gone by, before PCBs and digital stuff, when designers drew up schematics they'd often add construction notes or indicate where they'd used thicker wire. You don't see that these days so much. In the schematic below I've shown the effect of moving from layout 1 to layout 3 in post #19. That 'simple' layout change eliminates the bulk of the source parasitics effect on the gate drive and reduces the chances of oscillation or ringing. Whether you show it on the schematic is up to you. Other effects, such as the skin effect (where AC currents travel in the outer few micrometres of the conductor), may also dictate specific construction approaches which should be flagged on the schematic.

This last schematic illustrates some of those ideas (I've removed the parasitics):

You're welcome.Thank you for taking the time to show me the proper PCB layout I really appreciate that and all your help thus far.
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